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參數(shù)資料
| 型號： | CXD2587Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁數(shù)： | 12/106頁 |
| 文件大小： | 807K |
| 代理商： | CXD2587Q |
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CXD2587Q
Contents
§1. CPU Interface
§1-1.
§1-2.
§1-3.
§1-4.
CPU Interface Timing ........................................................................................................................ 13
CPU Interface Command Table ........................................................................................................ 13
CPU Command Presets .................................................................................................................... 23
Description of SENS Signals and Commands ................................................................................... 28
§2. Subcode Interface
§2-1.
80-bit Sub Q Readout ........................................................................................................................ 42
§3. Description of Other Functions
§3-1.
Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 45
§3-2.
Frame Sync Protection ...................................................................................................................... 46
§3-3.
Error Correction ................................................................................................................................. 46
§3-4.
DA Interface ....................................................................................................................................... 47
§3-5.
Digital Out .......................................................................................................................................... 49
§3-6.
Servo Auto Sequence ....................................................................................................................... 49
§3-7.
Digital CLV ......................................................................................................................................... 56
§3-8.
CD-DSP Block Playback Speed ........................................................................................................ 57
§3-9.
DAC Block Playback Speed .............................................................................................................. 57
§3-10. Description of DAC Block Functions .................................................................................................. 58
§3-11. LPF Block .......................................................................................................................................... 61
§3-12. Asymmetry Compensation ................................................................................................................ 62
§3-13. CD TEXT Data Demodulation ........................................................................................................... 63
§4. Description of Servo Signal Processing System Functions and Commands
§4-1.
General Description of Servo Signal Processing System .................................................................. 65
§4-2.
Digital Servo Block Master Clock (MCK) ........................................................................................... 66
§4-3.
AVRG Measurement and Compensation .......................................................................................... 66
§4-4.
E:F Balance Adjustment Function ..................................................................................................... 68
§4-5.
FCS Bias Adjustment Function .......................................................................................................... 68
§4-6.
AGCNTL Function ............................................................................................................................. 70
§4-7.
FCS Servo and FCS Search ............................................................................................................. 72
§4-8.
TRK and SLD Servo Control ............................................................................................................. 73
§4-9.
MIRR and DFCT Signal Generation .................................................................................................. 74
§4-10. DFCT Countermeasure Circuit .......................................................................................................... 75
§4-11. Anti-Shock Circuit .............................................................................................................................. 75
§4-12. Brake Circuit ...................................................................................................................................... 76
§4-13. COUT Signal ..................................................................................................................................... 77
§4-14. Serial Readout Circuit ........................................................................................................................ 77
§4-15. Writing to the Coefficient RAM .......................................................................................................... 78
§4-16. PWM Output ...................................................................................................................................... 78
§4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 80
§4-18. Description of Commands and Data Sets ......................................................................................... 80
§4-19. List of Servo Filter Coefficients .......................................................................................................... 95
§4-20. Filter Composition .............................................................................................................................. 97
§4-21. TRACKING and FOCUS Frequency Response .............................................................................. 104
§5. Application Circuit
.................................................................................................................................. 105
Explanation of abbreviations
AVRG:
AGCNTL: Auto gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
Average
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2588Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2588Q/R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD Digital Signal Processor with Built-in DigitalServo and DAC |
| CXD2588R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2589Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor |
| CXD2597Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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