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參數(shù)資料
| 型號： | CXD2585Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo |
| 中文描述： | CD數(shù)字信號處理器的內(nèi)置數(shù)碼舵機(jī) |
| 文件頁數(shù)： | 11/127頁 |
| 文件大小： | 962K |
| 代理商： | CXD2585Q |
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CXD2585Q
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing .................................................................................................................... 12
§ 1-2. CPU Interface Command Table .................................................................................................... 12
§ 1-3. CPU Command Presets ................................................................................................................ 23
§ 1-4. Description of SENS Signals......................................................................................................... 29
[2] Subcode Interface
§ 2-1. P to W Subcode Readout.............................................................................................................. 53
§ 2-2. 80-bit Sub-Q Readout.................................................................................................................... 53
[3] Description of Modes
§ 3-1. CLV-N Mode.................................................................................................................................. 60
§ 3-2. CLV-W Mode................................................................................................................................. 60
§ 3-3. CAV-W Mode................................................................................................................................. 60
§ 3-4. VCO-C mode................................................................................................................................. 61
[4] Description of Other Functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit ...................................................................... 64
§ 4-2. Frame Sync Protection.................................................................................................................. 66
§ 4-3. Error Correction............................................................................................................................. 66
§ 4-4. DA Interface................................................................................................................................... 67
§ 4-5. Digital Out...................................................................................................................................... 69
§ 4-6. Servo Auto Sequence.................................................................................................................... 70
§ 4-7. Digital CLV..................................................................................................................................... 78
§ 4-8. Playback Speed............................................................................................................................. 79
§ 4-9. Asymmetry Correction................................................................................................................... 80
§ 4-10. CD TEXT Data Demodulation ....................................................................................................... 81
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System.............................................................. 83
§ 5-2. Digital Servo Block Master Clock (MCK)....................................................................................... 84
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ....................................................... 85
§ 5-4. E: F Balance Adjustment Function ................................................................................................ 86
§ 5-5. FCS Bias Adjustment Function...................................................................................................... 86
§ 5-6. AGCNTL Function ......................................................................................................................... 88
§ 5-7. FCS Servo and FCS Search ......................................................................................................... 90
§ 5-8. TRK and SLD Servo Control ......................................................................................................... 91
§ 5-9. MIRR and DFCT Signal Generation.............................................................................................. 92
§ 5-10. DFCT Countermeasure Circuit...................................................................................................... 93
§ 5-11. Anti-Shock Circuit.......................................................................................................................... 93
§ 5-12. Brake Circuit.................................................................................................................................. 94
§ 5-13. COUT Signal ................................................................................................................................. 95
§ 5-14. Serial Readout Circuit.................................................................................................................... 95
§ 5-15. Writing to Coefficient RAM ............................................................................................................ 96
§ 5-16. PWM Output.................................................................................................................................. 96
§ 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 97
§ 5-18. Description of Commands and Data Sets ..................................................................................... 97
§ 5-19. List of Servo Filter Coefficients...................................................................................................... 117
§ 5-20. Filter Composition.......................................................................................................................... 119
§ 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 125
[6] Application Circuit
.................................................................................................................................. 126
Explanation of abbreviations AVRG:
Average
Auto gain control
Focus
Tracking
Sled
Defect
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
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| CXD2586R | CD Digital Signal Processor With Built-In Digital Servo and DAC(CD數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)和D/A轉(zhuǎn)換器）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2586R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2586R/-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD-Player Processor/Controller |
| CXD2586R-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2587 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2587Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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