參數(shù)資料
型號: CXD2510Q
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor
中文描述: CD數(shù)字信號處理器
文件頁數(shù): 1/48頁
文件大?。?/td> 743K
代理商: CXD2510Q
Description
The CXD2510Q is a digital signal processor LSI for
CD players and is equipped with the following functions.
Wide frame jitter margin (±28 frames) due to a built-
in 32K RAM
Bit clock, which strobes the EFM signal, is
generated by the digital PLL
EFM data demodulation
Enhanced EFM frame sync signal protection
Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Quadruple-speed, double-speed and variable pitch
playback
Noise reduction during track jumps
Auto zero-cross mute
Subcode demodulation and Sub Q data error
correction
Digital spindle servo (built-in oversampling filter)
16-bit traverse counter
Asymmetry compensation circuit
Serial bus-based CPU interface
Error correction monitor signals are output from a
new CPU interface.
Servo auto sequencer
Fine search which performs high-precision track
jumps
Digital audio interface output
Digital level meter, peak meter
Bilingual compatible
Features
All digital signals processed with a single chip
during playback
High-integrated mounting possible due to a built-in
RAM
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage
Input voltage
V
DD
V
I
–0.3 to +7.0
–0.3 to +7.0
V
V
(V
SS
– 0.3V to V
DD
+ 0.3V)
–0.3 to +7.0
–40 to +125 °C
Output voltage
Storage temperature Tstg
Supply voltage difference
V
O
V
Vss – AVss –0.3 to +0.3
V
DD
– AV
DD
–0.3 to +0.3
V
V
Recommended Operating Conditions
Supply voltage
Operating temperature Topr
The V
DD
(min.) for the CXD2510Q varies according
to the playback speed and built-in VCO selection.
The V
DD
(min.) is 4.50 V when high speed VCO
and quadruple-speed playback are selected
(variable pitch off). The V
DD
CXD2510Q under various conditions are as shown
in the following table.
V
DD
4.50 to 5.50
–20 to +75
V
°C
(min.) for the
Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
1
When the internal operation of the LSI is set to
normal-speed playback and the operating clock
of the signal processor is doubled, double-speed
playback results.
2
When the internal operation of the LSI is set to
double-speed mode and the crystal oscillating
frequency is halved in low power consumption
mode, normal-speed playback results.
Input/output Capacitances
Input capacitance
Output capacitance
C
I
C
O
12 (max.)
12 (max.)
for high impedance
V
DD
= V
I
= 0V
f
M
= 1MHz
pF
pF
Note)
Measurement conditions
– 1 –
CXD2510Q
E94412A11
CD Digital Signal Processor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
80 pin QFP (Plastic)
Playback
speed
V
DD
(min.) [V]
VCO high-speed
VCO normal-speed
×
4
×
2
1
×
2
×
1
×
1
2
4.50
4.00
3.40
3.40
3.40
4.00
3.40
3.40
-L01
-L051
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