參數(shù)資料
型號: CXA1871S
廠商: Sony Corporation
元件分類: 外設(shè)及接口
英文描述: Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????)
中文描述: 單電源RS232C接口線路驅(qū)動器/接收器(單電源RS232C接口線收發(fā)器(2發(fā)2收))
文件頁數(shù): 31/46頁
文件大?。?/td> 639K
代理商: CXA1871S
—31—
CXA1871S
Description of Operation
1. Synchronizing and picture distortion correction systems
The video signals (2 Vp-p standard) input to Pins 43 and 44 are led to the horizontal and vertical sync
separation circuits for sync separation.
This horizontal sync signal is compared with the signal obtained by 1/32 frequency dividing the 32 fh VCO
output using the ceramic oscillator (frequency: 503.5 kHz) to detect a phase difference. The error voltage
resulting from the phase difference is applied to the H oscillator after attenuating the medium and high
frequency components by a lag-lead filter. The phase of the H oscillator output is compared and shifted to
match the phase of the H deflection pulse (flyback pulse) input from Pin 34, and then output from Pin 32.
After the vertical sync signal is synchronized to the input signal by the V countdown system, a sawtooth
wave is generated by charging and discharging the capacitor attached externally to Pin 29. AGC is
performed to ensure that the amplitude of the sawtooth wave output is maintained constant regardless of
the vertical frequency of the input, after which the sawtooth wave passes through the picture distortion
correction circuit and is output from Pin 27.
Note that there is no need to adjust the free running frequency for either the H or V oscillator.
When voltage of 3 V or more is applied to Pin 33, the H drive output is held at low level. A time constant
circuit is included to protect against overvoltages, and H drive is output normally when high voltage input
continues for less than 7 V cycles. To release holddown, the IC must be turned off and then started up
again.
BGP, HBLK and VBLK are output to Pin 42 as SCP (Sand Cathle Pulse).
Note)
If external capacitance of Pin 30 is used with 0.1 μF or less of the recommended value, vertical sync output
may be unstable.
When changing the capacitance value, use it with 0.047 μF or more.
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