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參數(shù)資料
| 型號： | CSR2930800BA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FLASH MEMORY CMOS 8M (1M x 8/512K x 16) BIT |
| 中文描述： | 閃存的CMOS 800萬（100萬x 8/512K × 16）位 |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 475K |
| 代理商： | CSR2930800BA |
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CSR2930800BA
-90
23
14. RY/BY
Ready/Busy
The CSR2930800BA provide a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy
with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the CSR2930800BA are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “8. RY/BY Timing Diagram during Program/Erase Operations”
and “9. RESET/RY/BY Timing Diagram” in
I
SWITCHING WAVEFORMS for a detailed timing diagram. The RY/
BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
15. Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the CSR2930800BA devices. When this
pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to
DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer
to “10. Timing Diagram for Word Mode Configuration” and “11. Timing Diagram for BYTE Mode Configuration”
and “12. BYTE Timing Diagram for Write Operations” in
I
SWITCHING WAVEFORMS for the timing diagram.
16. Data Protection
The CSR2930800BA are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the devices automatically
reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
17. Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
18. Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
19. Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
20. Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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