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參數(shù)資料
| 型號： | CS8406-DZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XMITTER DGTL 192KHZ 28TSSOP |
| 標準包裝： | 50 |
| 類型： | 數(shù)字音頻接口發(fā)射器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 配用： | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 其它名稱： | 598-1722 |
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DS580F6
23
CS8406
8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.11 Interrupt 2 Mask (0Ch)
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.
8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.13 Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
76
5
4
3
2
1
0
TSLIP1
0
EFTC1
0
TSLIP0
0
EFTC0
0
76
5
4
3
2
1
0
00
0
EFTUM
0
76
5
4
3
2
1
0
00
0
EFTU1
0
00
0
EFTU0
0
76
5
4
3
2
1
0
0
BSEL
0
EFTCI
CAM
0
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| CS8427-DZZ | IC TXRX DGTL AUDIO 96KHZ 28TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8406-DZZR | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Transmitter RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| CS8406-IS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS8406-IZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS841 | 制造商:HVPSI 制造商全稱:High Voltage Power Solutions, Inc. 功能描述:MOV Modules |
| CS8411 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:DIGITAL AUDIO INTER FACE RECEIVER |
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