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參數(shù)資料
| 型號： | CS5533-ASZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 38/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2CH W/LNA 24-SSOP |
| 標(biāo)準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極；4 個差分，雙極 |
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CS5531/32/33/34-AS
DS289F5
43
2.12. Getting Started
This A/D converter has several features. From a
software programmer’s prospective, what should
be done first? To begin, a 4.9152 MHz or
4.096 MHz crystal takes approximately 20 ms to
start. To accommodate for this, it is recommended
that a software delay of approximately 20 ms start
the processor’s ADC initialization code. Next,
since the CS5531/32/33/34 do not provide a power-
on-reset function, the user must first initialize the
ADC to a known state. This is accomplished by re-
setting the ADC’s serial port with the Serial Port
Initialization sequence. This sequence resets the se-
rial port to the command mode and is accomplished
by transmitting 15 SYNC1 command bytes (0xFF
hexadecimal), followed by one SYNC0 command
(0xFE hexadecimal). Once the serial port of the
ADC is in the command mode, the user must reset
all the internal logic by performing a system reset
sequence (see 2.3.2 System Reset Sequence). The
next action is to initialize the voltage reference
mode. The voltage reference select (VRS) bit in the
configuration register must be set based upon the
magnitude of the reference voltage between the
VREF+ and the VREF- pins.
After this, the channel-setup registers (CSRs) should
be initialized, as these registers determine how cali-
brations and conversions will be performed. Once
the CSRs are initialized, the user has three options in
calibrating the ADC: 1) don’t calibrate and use the
default settings; 2) perform self or system calibra-
tions; or 3) upload previously saved calibration re-
sults to the offset and gain registers. At this point,
the ADC is ready to perform conversions.
2.13. PCB Layout
For optimal performance, the CS5531/32/33/34
should be placed entirely over an analog ground
plane. All grounded pins on the ADC, including the
DGND pin, should be connected to the analog
ground plane that runs beneath the chip. In a split-
plane system, place the analog-digital plane split
immediately adjacent to the digital portion of the
chip.
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參數(shù)描述 |
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| CS5534 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA |
| CS5534-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 24-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5534-ASR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 24-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5534-ASZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 24-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5534-ASZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 24-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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