參數(shù)資料
型號(hào)： CS5346-CQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 25/38頁(yè)
文件大小： 0K
描述： IC ADC AUD 103DB 200KHZ 48LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 250mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
輸入數(shù)目和類(lèi)型： 6 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 755 (CN2011-ZH PDF)
配用： 598-1790-ND - BOARD EVAL FOR CS5346
其它名稱(chēng)： 598-1692
DS861PP3
31
CS5346
7.7
Channel A PGA Control - Address 08h
7.7.1
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 10 for ex-
ample settings.
7.8
ADC Input Control - Address 09h
7.8.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 11.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on asignal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 11.
7
65
432
10
Reserved
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
Table 10. Example Gain and Attenuation Settings
7
65
432
10
Reserved
PGASoft
PGAZero
Sel2
Sel1
Sel0
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參數(shù)描述
CS5346-CQZR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 103dB 24B 192kHz Stereo Audio ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
CS5346-DQZ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5346-DQZR 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類(lèi)型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
CS5349-000 制造商:TE Connectivity 功能描述:4110-10-340812
CS5349-BP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit
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