參數(shù)資料
型號(hào)： CS5346-CQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 19/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC AUD 103DB 200KHZ 48LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 250mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
輸入數(shù)目和類型： 6 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 755 (CN2011-ZH PDF)
配用： 598-1790-ND - BOARD EVAL FOR CS5346
其它名稱： 598-1692
26
DS861PP3
CS5346
5.9
Reset
When RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the con-
trol port and registers, the outputs are muted. When RST is high, the control port becomes operational, and
the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Con-
trol register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended op-
erating condition to prevent power-glitch-related issues.
5.10 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the mast er clocks and left/ right clocks must be the same f or all of the
CS5346s in the system. If only one master clock source is needed, one solution is to place one CS5346 in
Master Mode, and slave all of the other CS5346s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS5346 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
5.11 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5346 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supplies (VLS or VLC). Power supply decoupling capacitors should be as near to the CS5346
as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS5346 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the CS5346 digital outputs only to CMOS inputs.
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參數(shù)描述
CS5346-CQZR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 103dB 24B 192kHz Stereo Audio ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
CS5346-DQZ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5346-DQZR 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
CS5349-000 制造商:TE Connectivity 功能描述:4110-10-340812
CS5349-BP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit
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