參數(shù)資料
型號: CS5346-CQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 22/38頁
文件大?。?/td> 0K
描述: IC ADC AUD 103DB 200KHZ 48LQFP
標(biāo)準(zhǔn)包裝: 250
位數(shù): 24
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 250mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
輸入數(shù)目和類型: 6 個(gè)單端,單極
產(chǎn)品目錄頁面: 755 (CN2011-ZH PDF)
配用: 598-1790-ND - BOARD EVAL FOR CS5346
其它名稱: 598-1692
DS861PP3
29
CS5346
7.3
ADC Control - Address 04h
7.3.1
Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
7.3.2
Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.
7.3.3
Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
7.3.4
High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DCOffset Calibration” on
7.3.5
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
7
65
432
10
FM1
FM0
Reserved
DIF
Reserved
Mute
HPFFreeze
M/S
FM1
FM0
Mode
0
Single-Speed Mode: 8 to 50 kHz sample rates
0
1
Double-Speed Mode: 50 to 100 kHz sample rates
1
0
Quad-Speed Mode: 100 to 200 kHz sample rates
11
Reserved
Table 6. Functional Mode Selection
DIF
Description
Format
Figure
0
Left-Justified (default)
0
1IS
1
Table 7. Digital Interface Formats
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