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參數(shù)資料
| 型號： | CS5322GDWR28 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 405K |
| 代理商： | CS5322GDWR28 |
CS5322
http://onsemi.com
15
the 30 μA charge current will allow the output to ramp up at
0.3 V/ms or 1.5 V in 5.0 ms at startup.
When a fault is detected due to overcurrent or UVLO the
converter will enter a low duty cycle hiccup mode. During
hiccup mode the converter will not switch from the time a
fault is detected until the Soft Start capacitor has discharged
below the Soft Start Discharge Threshold and then charged
back up above the Channel Start Up Offset.
The Soft Start pin will disable the converter when pulled
below 0.3 V.
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multilayer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
The current sense signal is typically tens of millivolts.
Noise pickup should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pickoff point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
DESIGN PROCEDURE
Current Sensing, Power Stage and
Output Filter Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
DVPEAK + (DI DT)
ESL ) DI
ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response.
Typically
both
bulk
capacitance
(electrolytic, Oscon, etc.,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
R + (VIN * VOUT)
VOUT VIN
F
C
25 mV
Then choose the inductor value and inherent
resistance to satisfy L/RL = R × C.
For ideal current sense compensation the ratio of L and
RL is fixed, so the values of L and RL will be a
compromise typically with the maximum value RL
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
3. For resistive current sensing choose L and RS to
provide a steady state ramp greater than 25 mV.
L RS + (VIN * VOUT)
TON 25 mV
Again the ratio of L and RL is fixed and the values of
L and RS will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(ΔVR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ΔVR should be less than the peak output
voltage overshoot or undershoot.
DVR + ConverterZ
ESR
ConverterZ +
PwrstgZ
ESR
PwrstgZ ) ESR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5322-KL | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Variable Bandwidth A/D Converter Chipset |
| CS5323 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three-Phase Buck Controller with 5-Bit DAC |
| CS5323/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Three-Phase Buck Controller with 5-Bit DAC |
| CS5323_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Buck Controller with 5−Bit DAC |
| CS5323-BL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
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