參數(shù)資料
型號(hào)： CS2100P-DZZR
廠商： CIRRUS LOGIC INC
元件分類(lèi)： PLL合成/DDS/VCOs
中文描述： PHASE LOCKED LOOP, 30 MHz, PDSO10
封裝： 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁(yè)數(shù)： 20/25頁(yè)
文件大小： 223K
代理商： CS2100P-DZZR
CS2100-OTP
4
DS841F2
1. PIN DESCRIPTION
Pin Name
#
Pin Description
VD
1
Digital Power (Input) - Positive power supply for the digital and analog sections.
GND
2
Ground (Input) - Ground reference.
CLK_OUT
3
PLL Clock Output (Output) - PLL clock output.
AUX_OUT
4
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on configuration.
CLK_IN
5
Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
XTO
XTI/REF_CLK
6
7
Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
M2
8
Mode Select (Input) - M2 is a configurable mode selection pin.
M1
9
Mode Select (Input) - M1 is a configurable mode selection pin.
M0
10
Mode Select (Input) - M0 is a configurable mode selection pin.
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
M2
M1
M0
AUX_OUT
CLK_IN
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