- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378459 > CS19203CBI20 (Applied Micro Circuits Corp.) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | CS19203CBI20 |
| 廠商： | Applied Micro Circuits Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 89K |
| 代理商： | CS19203CBI20 |
FINAL/PRODUCTION RELEASE
Information
- The information contained in this
document is about a product in its fully tested and characterized phase. All fea-
tures described herein are supported. Contact AMCC for updates to this docu-
ment and the latest product status.
Empowering Intelligent Optical Networks
Product Brief
HUDSON 2.0
Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device
Part Number S19203CBI20, Revision 1.3, May 2003
Core logic runs on a 1.8 V power supply to reduce power con-
sumption and LVCMOS I/O are 3.3 V compatible.
Two independent 16-bit parallel LVDS input and output ports at
up to 693.483 MHz (11.096 Gbps).
Datapath options: Configurable as two completely independent
data stream for full duplex operation. Configurable as a single
data stream for regenerator operation with dual redundant I/O for
optional protection switching. Either input port can be directly
connected to either output port for loopback testing or bypass
operation.
Supports SONET OC-192 Performance Monitoring at the input of
the encoder side and at the output of the decoder side.
Supports G.709 “Interfaces for the optical transport network
(OTN)” standard including specified frame structure, all overhead
monitoring and processing, Maintenance signals, synchronous
and asynchronous mapping and demapping.
ON/OFF control of Reed-Solomon (255,239) FEC Encoding/
Decoding and error correction.
Support for System test and diagnostics: internal BER generator,
PRBS pattern generator and pattern analyzer for bit error rate
testing capability.
Four programmable integer clock dividers to simplify clock gener-
ation.
Support for signal aggregation to higher rates via chip synchroni-
zation feature.
General Purpose Processor Interface: Gluess interface to
MPC860, 25 MHz to 50 MHz bus speed. Also compatible with
Intel microprocessor bus via Busmode selector.
Low power: 0.18 micron CMOS technology.
Applications
10 Gigabit Digital Wrapper Performance Monitor and Framer
Protocol Independent DWDM Metropolitan Area Networks
Optical Cross-connects
OC-192 Port interface
Fiber optic terminators, repeaters, and test equipment
The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC)
device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The
Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the
device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate
from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed,
descrambled and scrambled, and decoded and encoded with forward error correction information.
Figure 1: Block Diagram
DECODEIN[15:0]
DUPLEXOUT[15:0]
DEC OH
Mon/Drop
FEC
Decoder
DEC
1:8
Demux
DUPO
UT 1:8
Mux
DEC
SONET
PM
Decode (DEC) Side
DUPTXCLK_OUT
DECRXCLK
Rate
Match
FIFO
Pattern
Analyzer
ENC
8:1
Mux
ENC OH
Frame
Gen &
FEC
Encoder
ENCDATAOUT[15:0]
ENCTXCLK
ENC OH
Add
TX_OH_CLK
TX_OINSSFP
TX_OH_INS
DUPIN
1:8
Demux
DUPLEXIN[15:0]
DUPRXCLK
Encode (ENC) Side
Rate
Match
FIFO
Pattern
Generator
DUP OH
Framer
DEC OH
Framer
OCH
Descram
& SC/OH
Mon/Drop
DEC OH
Ins &
Scrambler
DEC_INSCLK
DEC_INS_FP
DEC_INS_SFP
DECINS[7:0]
DEC_INS_EN
Hudson 2.0
RX_OH_CLK
RX_OH_DATA[7:0]
DROPFP
DROPSFP
ENC_DRPCLK
ENC_DRP[7:0]
ENC_DRP_FP
ENC_DRP_SFP
Clock
Divider
DECRXCLK_DIV
Clock
Divider
DUPRXCLK_DIV
Clock
Divider
ENCTXCLK_DIV
Clock
Divider
DUPTXCLK_DIV
ENC
SONET
PM
Sync
Buffer
INPUT_PORT_SW AP
INPUT_PORT_SW AP
DEC_IN_SEL[1:0]
PAT_GEN_ON
DUP_OUT_SEL[1:0]
OUTPUT_PORT_SW AP
ENC_IN_SEL
ENC_OUT_SEL[1:0]
OUTPUT_PORT_SW AP
0
1
1
0
00
10
01
01
01, 11
00
11
00
10
10
00, 01
10
00
01
0
0
1
1
0
0
1
1
00,10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS19233 | 10 G Ethernet/Fibre Channel/SONET/SDH Dual CDR |
| CS19 | Phase Control Thyristor |
| CS20-22MOF1 | High Voltage Phase Control Thyristorin High Voltage ISOPLUS i4-PAC-TM |
| CS2036 | Open Fiber Control |
| CS2060 | Gigabit Ethernet/Fibre Channel Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS19204CBI12 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:SONET/SDH STS-192/STM-64 MUX/DEMUX with Pointer Processor |
| CS19205CBI | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper |
| CS19208CBI | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device |
| CS19223CBI11 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:SONET/SDH STS-192/STM-64 MUX/DEMUX with Pointer Processor |
| CS19227PBI | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:10GE & OC192/48/12/3 DW/FEC/PM and AsyncMap Device with Strong FEC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。