參數(shù)資料
型號(hào)： COP8SGR728Q3XXX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, MICROCONTROLLER, CDIP28
封裝： WINDOWED, DIP-28
文件頁(yè)數(shù)： 9/62頁(yè)
文件大小： 840K
代理商： COP8SGR728Q3XXX
5.0 Functional Description (Continued)
Syntax:
[label:] .sect
econ, conf
.db
value
;1 byte,
;configures options
.db
<user information>
.endsect
; up to 8 bytes
Example: The following sets a value in the ECON register
and User Identification for a COP8SGR728M7. The ECON
bit values shown select options: Power-on enabled, Security
disabled, Crystal oscillator with on-chip bias disabled,
WATCHDOG enabled and HALT mode enabled.
.sect
econ, conf
.db
0x55
;por, xtal, wd, halt
.db
'my v1.00' ;user data declaration
.endsect
5.7 OTP SECURITY
The device has a security feature that, when enabled, pre-
vents external reading of the OTP program memory. The
security bit in the ECON register determines, whether secu-
rity is enabled or disabled. If the security feature is disabled,
the contents of the internal EPROM may be read.
If the security feature is enabled, then any attempt to
externally read the contents of the EPROM will result in
the value FF Hex being read from all program locations
Under no circumstances can a secured part be read. In
addition, with the security feature enabled, the write opera-
tion to the EPROM program memory and ECON register is
inhibited. The ECON register is readable regardless of the
state of the security bit. The security bit, when set, cannot
be erased, even in windowed packages. If the security bit
is set in a device in a windowed package, that device may be
erased but will not be further programmable.
If security is being used, it is recommended that all other bits
in the ECON register be programmed first. Then the security
bit can be programmed.
5.8 ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that era-
sure begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (). It should be
noted that sunlight and certain types of fluorescent lamps
have wavelengths in the 3000 - 4000 range.
After programming, opaque labels should be placed over the
window of windowed devices to prevent unintentional era-
sure. Covering the window will also prevent temporary func-
tional failure due to the generation of photo currents.
The recommended erasure procedure for windowed devices
is exposure to short wave ultraviolet light which has a wave-
length of 2537 Angstroms (). The integrated dose (i.e. UV
intensity X exposure time) for erasure should be a minimum
of 15W-sec/cm2.
5.9 RESET
The devices are initialized when the RESET pin is pulled low
or the On-chip Power-On Reset is enabled.
The following occurs upon initialization:
Port L: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T2CNTRL: CLEARED
T3CNTRL: CLEARED
Accumulator, Timer 1, Timer 2 and Timer 3:
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
Initialized to RAM address 06F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
S Register: CLEARED
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
USART:
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
COMPARATORS:
CMPSL; CLEARED
WATCHDOG (if enabled):
The device comes out of reset with both the WATCH-
DOG logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
C clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
DS101317-13
FIGURE 9. Reset Logic
COP8SG
Family
www.national.com
17
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