
Functional Description
(Continued)
Upon initialization, the PC register is cleared to 0 (ROM ad-
dress 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at ad-
dress 0 must be a CLRA.
TL/DD/6919–8
Ceramic Resonator Oscillator
Resonator
Value
Components Values
R1 (
X
)
R2 (
X
)
C1 (pF)
C2 (pF)
455 kHz
4.7k
1M
220
220
RC Controlled Oscillator
Instruction
Cycle Time
in
m
s
R (k
X
)
C (pF)
51
82
100
56
19
g
15%
19
g
13%
Note:
200k
X
t
R
t
25k
X
.360pF
t
C
t
50pF.Doesnotincludetolerances.
FIGURE 6. COP410L/411L Oscillator
OSCILLATOR
There are three basic clock oscillator configurations avail-
able as shown by Figure 6.
a. Resonator Controlled Oscillator.
CKI and CKO are
connected to an external ceramic resonator. The instruc-
tion cycle frequency equals the resonator frequency di-
vided by 8. This is not available in the COP411L.
b. External Oscillator.
CKI is an external clock input signal.
The external frequency is divided by 4 to give the instruc-
tion frequency time. CKO is now available to be used as
the RAM power supply (V
R
), or no connection.
Note:
No CKO on COP411L.
c. RC Controlled Oscillator.
CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruc-
tion cycle equals the oscillation frequency divided by 4.
CKO is available as the RAM power supply (V
R
) or no
connection.
CKO PIN OPTIONS
In a resonator controlled oscillator system, CKO is used as
an output to the resonator network. As an option, CKO can
be a RAM power supply pin (V
R
), allowing its connection to
a standby/backup power supply to maintain the integrity of
RAM data with minimum power drain when the main supply
is inoperative or shut down to conserve power. Using no
connection option is appropriate in applications where the
COP410L system timing configuration does not require use
of the CKO pin.
RAM KEEP-ALIVE OPTION
Selecting CKO as the RAM power supply (V
R
) allows the
user to shut off the chip power supply (V
CC
) and maintain
data in the RAM. To insure that RAM data integrity is main-
tained, the following conditions must be met:
1. RESET must go low before V
CC
goes below spec during
power-off; V
CC
must be within spec before RESET goes
high on power-up.
2. During normal operation, V
R
must be within the operating
range of the chip with (V
CC
b
1)
s
V
R
s
V
CC
.
3. V
R
must be
t
3.3V with V
CC
off.
I/O OPTIONS
COP410L/411L inputs and outputs have the following op-
tional configurations, illustrated in Figure 7:
a. Standard
Dan enhancement-mode device to ground in
conjunction with a depletion-mode device to V
CC
, com-
patible with LSTTL and CMOS input requirements. Avail-
able on SO, SK, and all D and G outputs.
b. Open-Drain
Dan enhancement-mode device to ground
only, allowing external pull-up as required by the user’s
application. Available on SO, SK, and all D and G out-
puts.
c. Push-Pull
Dan enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to V
CC
. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
d. Standard L
Dsame as
a.
, but may be disabled. Available
on L outputs only.
e. Open Drain L
Dsame as
b.
, but may be disabled. Avail-
able on L outputs only.
f. LED Direct Drive
Dan enhancement mode device to
ground and to V
CC
, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (see
Functional Description, EN Register), placing the outputs
in a high-impedance state to provide required LED seg-
ment blanking for a multiplexed display. Available on L
outputs only.
Note:
Series current limiting resistors must be used if LEDs are driven di-
rectly and higher operating voltage option is selected.
g. TRI-STATE Push-Pull
Dan enhancement-mode device
to ground and V
CC
. These outputs are TRI-STATE out-
puts, allowing for connection of these outputs to a data
bus shared by other bus drivers. Available on L outputs
only.
9