參數(shù)資料
型號： CM17699
廠商： 意法半導體
英文描述： COLOR PDP DRIVER MODULE
中文描述： 彩色PDP驅動模塊
文件頁數(shù)： 9/11頁
文件大小： 250K
代理商： CM17699
6.6.3 - AC Timings Requirements
(V
CC
= 4.5V to 5.5V, T
amb
= -20 to +85°C, input signals max leading edge & trailing edge (t
R
, t
F
) = 10ns)
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
CLK
Data Clock Period
50
-
-
ns
t
WHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
t
WLCLK
Duration of clock (CLK) pulse at low level
15
-
-
ns
t
SDAT
Set-up Time of data input before clock (low to high) transition
0
-
-
ns
t
HDAT
Hold Time of data input after clock (low to high) transition
15
-
-
ns
t
DSTB
Minimum Delay to latch (STB) after clock (low to high) transition
20
-
-
ns
t
STB
Latch (STB) Low Level Pulse Duration
10
-
-
ns
t
BLK
Blanking (BLK) Pulse Duration
100
-
-
ns
t
POL
Polarity (POL) Pulse Duration
100
-
-
ns
t
HIZ
High Impedance (HIZ) Pulse Duration
100
-
-
ns
t
SFR
Set-up Time of ForwardReverse Signal before Clock (low to high) transition
100
-
-
ns
6.6.4 - AC Timings Characteristics
(V
CC
= 5V, V
PP
= 65V, V
SSP
= 0V, V
SSLOG
= 0V, V
SSSUB
= 0V, T
amb
= 25°C, V
ILMax.
= 0.2V
CC
, V
IHMin.
= 0.8V
CC
,
V
OH
= 4.0V, V
OL
= 0.4V, C
L
= 10pF, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
CLK
Data Clock Period
50
-
-
ns
t
RDAT
Logical Data Output Rise Time
-
TBD
30
ns
t
FDAT
Logical Data Output Fall Time
-
TBD
30
ns
t
PHL1
t
PLH1
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
-
-
40
40
TBD
TBD
ns
ns
t
PHL2
t
PLH2
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
-
TBD
TBD
120
120
ns
ns
t
PHL3
t
PLH3
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
-
TBD
TBD
110
110
ns
ns
t
PHL4
t
PLH4
Delay of power output change (high to low transition) to Blank (BLK) or Polarity
(POL) transition
Delay of power output change (low to high transition) to Blank (BLK) or Polarity
(POL) transition
-
-
TBD
TBD
100
100
ns
ns
t
PHZ5
t
PLZ5
Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5)
Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5)
-
-
TBD
TBD
100
100
ns
ns
t
PZH5
t
PZL5
Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5)
Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5)
-
-
TBD
TBD
100
100
ns
ns
t
ROUT
Power Output Rise Time (6)
-
-
150
ns
t
FOUT
Power Output Fall Time (6)
-
-
150
ns
Notes : 5. See test diagram.
6. One output among 64, loading capacitor C
OUT
= 50pF, other outputs at low level.
6 - STV7699 SPECIFICATIONS
(continued)
CM17699
9/11
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