Gain Register The gain register span is from 0 to (4-2-22). Af" />
參數(shù)資料
型號： CDB5529
廠商： Cirrus Logic Inc
文件頁數(shù)： 10/31頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR CS5529
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 303
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 2.6mW @ 2.5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5529
已供物品： 板，線纜，磁盤
產(chǎn)品目錄頁面： 755 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： CS5529-ASZR-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP
598-1110-5-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP
其它名稱： 598-1015
CS5529
18
DS246F5
Gain Register
The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is ‘1’, all other bits are ‘0’.
The gain calibration results is stored in the gain
register. The result sets the slope of the ADC’s
transfer function. The gain register spans from 0 to
(4 - 2-22). The decimal equivalent meaning of the
gain register is
where the binary numbers have a value of either
zero or one (b0 corresponds to bit MSB-1, N = 22).
Self Calibration
The CS5529 offers both self offset and self gain
calibrations. For the self-calibration of offset, the
converter internally ties the inputs of the modulator
together and routes them to the VREF- pin as
shown in Figure 6. Also self offset calibration re-
quires that VREF- be tied to a fixed voltage be-
tween VA+ and VA-. For self-calibration of gain,
the differential inputs of the modulator are connect-
ed to VREF+ and VREF- as shown in Figure7.
System Calibration
For the system calibration functions, the user must
input signals which represent system ground and
system full scale to the converter. When a system
offset calibration is performed a ground reference
signal must be applied to the converter (see Figure
8). When a system gain calibration is performed,
the user must input a signal representing the posi-
tive full scale point as shown in Figure 9. In either
case, calibration signals must be within the speci-
fied calibration limits for each specific calibration
step (refer to the System Calibration Specifica-
23(MSB)
22
21
20
19
18
17
16
15
14
13
12
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
0
00000
0
11
10
9876
5
4
3
2
1
0
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
0
00000
0
Db
MSB
2
1
b
(
0
2
0
b
1
2
1
–
… b
N
2
N
– )
++
+
b
MSB
2
1
b
i
2
i
–
i
0
=
N
∑
+
==
AIN+
AIN-
S1
OPEN
+
-
S2
OPEN
S4
CLOSED
VREF-
S3
CL
O
SED
Figure 6. Self Calibration of Offset.
AIN+
AIN-
OPEN
+
-
OPEN
CLOSED
VREF+
CLOSED
VREF-
+
-
Reference
Figure 7. Self Calibration of Gain.
+
-
External
Connections
0V +
-
AIN+
AIN-
Figure 8. System Calibration of Offset.
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