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參數(shù)資料
| 型號： | CBTL03SB212BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | DisplayPort Gen2 sideband signal multiplexer |
| 中文描述： | MULTIPLEXER, PQCC20 |
| 封裝： | 4 X 4 MM, 0.85 MM HEIGHT, PLASITC, MO-220, HVQFN-20 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 131K |
| 代理商： | CBTL03SB212BS |
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
4 of 16
NXP Semiconductors
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
6.2 Pin description
[1]
HVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the printed-circuit board in the thermal pad region.
Table 2.
Pin description
Symbol
Pin
Type
Description
SEL
5
3.3 V CMOS
single-ended input
Selects between two multiplexer/switch paths.
XSD_N
15
3.3 V CMOS
single-ended input
Shutdown pin. Should be driven HIGH or
connected to VDD for normal operation. When
LOW, all paths are switched off (non-conducting
high-impedance state), and supply current
consumption is minimized.
AUX+
20
differential I/O
High-speed differential pair for AUX signals,
right-side.
AUX
1
differential I/O
DDC_CLK
2
differential I/O
Pair of single-ended terminals for DDC clock and
data signals, right-side.
DDC_DAT
3
differential I/O
HPD
4
single-ended I/O
Single-ended channel for the HPD signal,
right-side.
AUX1+
17
differential I/O
High-speed differential pair for AUX signals, path 1,
left-side.
AUX1
16
differential I/O
AUX2+
14
differential I/O
High-speed differential pair for AUX signals, path 2,
left-side.
AUX2
13
differential I/O
DDC_CLK1
12
differential I/O
Pair of single-ended terminals for DDC clock and
data signals, path 1, left-side.
DDC_DAT1
11
differential I/O
DDC_CLK2
9
differential I/O
Pair of single-ended terminals for DDC clock and
data signals, path 2, left-side.
DDC_DAT2
8
differential I/O
HPD_1
10
single-ended I/O
Single-ended channel for the HPD signal, path 1,
left-side.
HPD_2
7
single-ended I/O
Single-ended channel for the HPD signal, path 2,
left-side.
VDD
6, 18
power supply
3.3 V power supply.
19
ground
Ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CBTL03SB212BS,515 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Gen 2 3CH Sideband Signal Multiplexer RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL04082A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CBTL04082A/B is an 8-to-4 bidirectional differential channel multiplexer/demultiplexer switch for PCI Express Generation 2 (Gen2) applications. |
| CBTL04082ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CBTL04082A/B is an 8-to-4 bidirectional differential channel multiplexer/demultiplexer switch for PCI Express Generation 2 (Gen2) applications. |
| CBTL04082ABS,518 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3.3V WD BW 4 DIFF CH 2:1 MULTI/DEMUX SW RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL04082BBS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CBTL04082A/B is an 8-to-4 bidirectional differential channel multiplexer/demultiplexer switch for PCI Express Generation 2 (Gen2) applications. |
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