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參數(shù)資料
| 型號： | CAT64LC40UATE13 |
| 英文描述： | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC40UATE13 |
5
CAT64LC10/20/40
Doc. No. 1021, Rev. A
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write
64LC10
10100100
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write Enable
10100011
X X X X X X X X
Write Disable
10100000
X X X X X X X X
[Write All Locations]
(1)
10100001
X X X X X X X X
D15–D0
Figure 1. A.C. Testing Input/Output Waveform
(2)(3(4)
(C
L
= 100 pF)
Note:
(1)
(2)
(3)
(4)
(Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
Input Rise and Fall Times (10% to 90%) < 10 ns.
Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
INPUT PULSE LEVELS
REFERENCE POINTS
VCC x 0.7
VCC x 0.3
VCC x 0.8
VCC x 0.2
相關PDF資料 |
PDF描述 |
|---|---|
| CAT64LC40UITE13 | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture |
| CAT64LC40URATE13 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CAT64LC40URITE13 | EEPROM |
| CAT64LC40URTE13 | EEPROM |
| CAT64LC40UTE13 | 72-Mbit QDR™-II SRAM 2-Word Burst Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC40U-GT3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40UI-GT3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40UI-T3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40UITE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
| CAT64LC40URATE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
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