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參數(shù)資料
| 型號(hào)： | CAT64LC10J-TE13 |
| 英文描述： | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC10J-TE13 |
9
CAT64LC10/20/40
Doc. No. 1021, Rev. A
RESET
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High-
Z condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/
BSY
pin and on
the DO pin if
CS
is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
ERASE/WRITE ENABLE and DISABLE
The CAT64LC10/20/40 powers up in the erase/write
disabled state. After power-up or while the device is in an
erase/write disabled state, any write operation must be
preceded by an execution of the EWEN instruction.
Once enabled, the device will stay enabled until an
EWDS has been executed or a power-down has occured.
The EWDS is used to prevent any inadvertent over-
writing of the data. The EWEN and EWDS instructions
have no affect on the READ operation and are not
affected by the RESET input.
Figure 8. EWDS Instruction Timing
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
SK
DI
CS
DO
RESET
1
0
1
0
0
0
0
0
HIGH-Z
HIGH
RDY/
BUSY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC10J-TE7 | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10P | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10P-2.5 | 2K x 8 Static RAM |
| CAT64LC10PA | 2K x 8 Static RAM |
| CAT64LC10PI | 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC10J-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC10L | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64 X 16 1K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT64LC10LATE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
| CAT64LC10LI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64 X 16 1K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT64LC10LITE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
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