參數(shù)資料
型號: CAT64LC10J-TE13
英文描述: 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: SPI串行EEPROM
文件頁數(shù): 3/11頁
文件大?。?/td> 140K
代理商: CAT64LC10J-TE13
3
CAT64LC10/20/40
Doc. No. 1021, Rev. A
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Note:
(1) Standby Current (I
SB
) = 0
μ
A (<900nA)
(2) V
OH
and V
OL
spec applies to READY/
BUSY
pin also
Limits
Sym.
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
Operating Current
2.5V
0.4
mA
f
SK
= 250 kHz
EWEN, EWDS, READ 6.0V
1
mA
f
SK
= 1 MHz
I
CCP
Program Current
2.5V
2
mA
6.0V
3
mA
I
SB(1)
Standby Current
0
μ
A
V
IN
= GND or V
CC
CS = V
CC
I
LI
Input Leakage Current
2
μ
A
μ
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
V
OUT
= GND to V
CC
V
IL
Low Level Input Voltage, DI
–0.1
V
CC
x 0.3
V
V
IH
High Level Input Voltage, DI
V
CC
x 0.7
V
CC
+ 0.5
V
V
IL
Low Level Input Voltage,
CS
, SK, RESET
–0.1
V
CC
x 0.2
V
V
IH
High Level Input Voltage,
CS
, SK, RESET
V
CC
x 0.8
V
CC
+ 0.5
V
V
OH(2)
High Level Output Voltage
2.5V
V
CC
– 0.3
V
I
OH
= –10
μ
A
I
OH
= –10
μ
A
I
OH
= –400
μ
A
I
OL
= 10
μ
A
6.0V
V
CC
– 0.3
V
2.4
V
V
OL(2)
Low Level Output Voltage
2.5V
0.4
V
6.0V
0.4
V
I
OL
= 2.1mA
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