VDD
參數(shù)資料
型號： CAT5172TBI-00GT3
廠商： ON Semiconductor
文件頁數(shù)： 4/10頁
文件大?。?/td> 0K
描述： IC POT DGTL 100K 256TAP SOT23-8
標(biāo)準(zhǔn)包裝： 3,000
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 100 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8
供應(yīng)商設(shè)備封裝： SOT-23-8
包裝： 帶卷 (TR)
CAT5172
http://onsemi.com
3
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; –40C < TA < +85C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
(Note 3)
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 4)
RWB, VA = no connection
RDNL
1
0.1
+1
LSB
Resistor Integral Nonlinearity (Note 4)
RWB, VA = no connection
RINL
2
0.4
+2
LSB
Nominal Resistor Tolerance (Note 5)
TA = 25C
nRAB
20
+20
%
Resistance Temperature Coefficient
VAB = VDD, Wiper = no connection
nRAB/nT
100
ppm/C
Wiper Resistance
VDD = 5 V
RW
50
120
W
VDD = 3 V
100
250
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution
N
8
Bits
Differential Nonlinearity (Note 6)
DNL
1
0.1
+1
LSB
Integral Nonlinearity (Note 6)
INL
1
0.4
+1
LSB
Voltage Divider Temperature Coefficient
Code = 0x80
nVW/nT
100
ppm/C
Full-Scale Error
Code = 0xFF
VWFSE
3
1
0
LSB
Zero-Scale Error
Code = 0x00
VWZSE
0
1
3
LSB
RESISTOR TERMINALS
Voltage Range (Note 7)
VA,B,W
GND
VDD
V
Capacitance (Note 8) A, B
f = 1 MHz, measured to GND,
Code = 0 x 80
CA,B
45
pF
Capacitance (Note 8) W
f = 1 MHz, measured to GND,
Code = 0 x 80
CW
60
pF
Common-Mode Leakage (Note 8)
VA = VB = VDD/2
ICM
1
nA
DIGITAL INPUTS
Input Logic High
VDD = 5 V
VIH
0.7 x VDD
V
Input Logic Low
VDD = 5 V
VIL
0.3VDD
V
Input Logic High
VDD = 3 V
VIH
0.7 x VDD
V
Input Logic Low
VDD = 3 V
VIL
0.3VDD
V
Input Current
VIN = 0 V or 5 V
IIL
1
mA
Input Capacitance (Note 8)
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
VIH = 5 V or VIL = 0 V
IDD
0.3
2
mA
Power Dissipation (Note 9)
VIH = 5 V or VIL = 0 V, VDD = 5 V
PDISS
0.2
mW
Power Supply Sensitivity
nVDD = +5 V 10%, Code = Midscale
PSS
0.05
%/%
3. Typical specifications represent average readings at +25C and VDD = 5 V.
4. Resistor position nonlinearity error RINL is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. RDNL measures the relative step change from ideal between successive tap positions. Parts are
guaranteed monotonic.
5. VAB = VDD, Wiper (VW) = no connect.
6. INL and DNL are measured at VW with the digital POT configured as a potentiometer divider similar to a voltage output D/A converter.
VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8. Guaranteed by design and not subject to production test.
9. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
10.All dynamic characteristics use VDD = 5 V.
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