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參數(shù)資料
| 型號(hào)： | CAT5172TBI-00GT3 |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 100K 256TAP SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 100 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
CAT5172
http://onsemi.com
9
Table 8. CODES AND CORRESPONDING RWA
RESISTANCE FOR RAB = 100 kW, VDD = 5 V
D (Dec.)
RWA (W)
Output State
255
441
Full Scale
128
50,050
Midscale
1
99,659
1 LSB
0
100,050
Zero Scale
Typical device to device resistance matching is lot
dependent and may vary by up to 20%.
SPI Compatible 3-wire Serial Bus
Control of CAT5172 is through a 3-wire SPI compatible
digital interface (SDI, CS, and CLK).
The CLK input is rising-edge sensitive and requires crisp
transitions to avoid clocking incorrect data into the serial
input register. When CS is low, the clock loads data into the
serial register on each positive clock edge (Figure 1). Each
8-bit serial word must be loaded starting with the MSB. The
format of the word is shown in Table 6.
Data loaded into CAT5172’s 8-bit serial input register is
transferred to the internal Wiper register when the CS line
returns to logic high. Extra MSB bits are ignored.
ESD Protection
GND
LOGIC
Digital
Input
GND
Potentiometer
Figure 15. ESD Protection Networks
Terminal Voltage Operating Range
The CAT5172 VDD and GND power supply define the
limits for proper 3-terminal digital potentiometer operation.
Signals or potentials applied to terminals A, B or the wiper
must remain inside the span of VDD and GND. Signals
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
W, A, B
CAT5172
LOGIC
GND
Figure 16.
VDD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 15), it is
recommended that VDD/GND be powered before applying
any voltage to terminals A, B, and W. The ideal power-up
sequence is: GND, VDD, digital inputs, and then VA/B/W. The
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01
mF to
0.1
mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
CAT5172
GND
+
10 mF
0.1 mF
Figure 17. Power Supply Bypassing
VDD
C3
C1
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