參數(shù)資料
型號(hào): CAT28F001PI-12B
廠商: ON SEMICONDUCTOR
元件分類: PROM
英文描述: 128K X 8 FLASH 12V PROM, 120 ns, PDIP32
封裝: PLASTIC, DIP-32
文件頁(yè)數(shù): 4/18頁(yè)
文件大小: 111K
代理商: CAT28F001PI-12B
CAT28F001
12
Doc. No. MD-1078, Rev. K
2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Bus
Operation
Command
Comments
Write
Erase
Data = 20H
Setup
Address = Within Block to be erased
Write
Erase
Data - D0H
Address = Within Block to be erased
Read
Status Register Data.
Toggle OE or CE to update
Status Register
Standby
Check SR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full Status check can be done after each block or after a sequence
of blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
Bus
Operation
Command
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during a erase attempt, before further
attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Figure 5 Block Erase Flowchart
START
WRITE 20H,
BLOCK ADDRESS
READ STATUS
REGISTER
SR.7 = 1?
FULL STATUS
CHECK IF DESIRED
BLOCK ERASE
COMPLETED
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
SR.5 = 0?
BLOCK ERASE
SUCCESSFUL
NO
WRITE D0H
BLOCK ADDRESS
FULL STATUS CHECK PROCEDURE
NO
VPP RANGE
ERROR
BLOCK ERASE
ERROR
SR.4,5 = 1?
YES COMMAND SEQUENCE
ERROR
SUSPEND
ERASE?
NO
ERASE SUSPEND
LOOP
YES
NO
YES
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