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參數(shù)資料
| 型號： | CAT1163J-30TE13 |
| 英文描述： | Supervisory Circuit with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer |
| 中文描述： | 監(jiān)控電路與I2C串行CMOS EEPROM的，精密復(fù)位控制器和看門狗定時器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 69K |
| 代理商： | CAT1163J-30TE13 |
5
CAT1163
Doc No. 3003, Rev. C
PIN DESCRIPTIONS
WDI:
If there is no transition on the WDI for more than 1.6
seconds, the watchdog timer times out.
WATCHDOG INPUT
WP:
If the pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
WRITE PROTECT
RESET/
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
down resistor and the
RESET
pin must be connected
through a pull-up resistor.
RESET
: RESET I/O
SDA:
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SERIAL DATA ADDRESS
SCL:
Serial clock input.
SERIAL CLOCK
DEVICE OPERATION
Reset Controller Description
The CAT1163 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power-up, the RESET outputs remain
active until V
CC
reaches the V
TH
threshold and will continue
driving the outputs for approximately 200ms (t
PURST
) after
reaching V
TH
. After the t
PURST
timeout interval, the device will
cease to drive the reset outputs. At this point the reset
outputs will be pulled up or down by their respective pull up/
down resistors. During power-down, the RESET outputs will
be active when V
CC
falls below V
TH
. The RESET outputs will
be valid so long as V
CC
is >1.0V (V
RVALID
).
The RESET pins are I/Os; therefore, the CAT1163 can act as
a signal conditioning circuit for an externally applied reset.
The inputs are edge triggered; that is, the RESET input in the
CAT1163 will initiate a reset timeout after detecting a low to
high transition and the
RESET
input in the CAT1163 will
initiate a reset timeout after detecting a high to low transition.
Watchdog Timer
The Watchdog Timer provides an independent protection for
microcontrollers. During a system failure, the CAT1163 will
respond with a reset signal after a time-out interval of 1.6
seconds for a lack of activity. The CAT1163 is designed with
a WDI input pin for the Watchdog Timer function. If the
microcontroller does not toggle the WDI input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
Figure 1. RESET Output Timing
GLITCH
t
V
CC
PURST
t
PURST
t
RPD
t
RVALID
V
V
TH
RESET
RESET
RPD
t
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT1163J-42 | 功能描述:監(jiān)控電路 16K I2C Memory w/WDT RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1163J-45 | 制造商:Catalyst Semiconductor 功能描述: |
| CAT1163J-45-TE13 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT1163J45-TE13 | 制造商:ON Semiconductor 功能描述:Processor Supervisor 3V/3.3V/5V 8-Pin SOIC N T/R |
| CAT1163JI-28 | 功能描述:監(jiān)控電路 16K I2C Memory w/WDT RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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