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參數(shù)資料
| 型號： | C9914BY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 131K |
| 代理商： | C9914BY |
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07069 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 4 of 14
http://www.cypress.com
PRELIMINARY
C9914
Power Management Functions (Cont.)
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running
after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior
to turning off the VCO’s and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency
should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are
considered to be don’t cares during the power down operations.
Power Management Timing
Latency
Signal
Signal State
No. of rising edges of free running PCI
CLOCK (PCIF)
CS#
0 (disabled)
1
1 (enabled)
1
PD#
1 (cold start/normal operation)
3 mS
0 (power down)
1
NOTES: Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the
first valid clock comes out of the device.
Power on Bi-Directional Pins
Power Up Condition:
Pins 14, 26, and 27 are Power up bi-directional pins and are used for different features in this device (see Pin description,
Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered input select
pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and these pins
become toggling clock outputs.
-
Hi-Z Inputs
Toggle Outputs
Power Supply
Ramp
Select Data is latched into register then pin becomes clock output signal.
VDD Rail
48_24MHz/HFS#
REF1/SS#
REF2/SEL48#
Fig. 2
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