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參數(shù)資料
| 型號(hào)： | C9914BY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | C9914BY |
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Clock Generator for 100MHz and 133.3MHz Mobile Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07069 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 3 of 14
http://www.cypress.com
PRELIMINARY
C9914
Power Management Functions
PS#
CS#
PD#
CPU (1:2)
48M, 48_24M
PCI (1:5)
PCI_F
REF (1:2)
VCOs
X
0
LOW
OFF
1
0
1
LOW
ON
0
1
ON
LOW
ON
0
1
LOW
ON
LOW
ON
1
ON
ONON
CS# is the CPU stop control pin. It is used to turn off the CPU clocks for low power operation. CS# is asserted
asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU
clocks are disabled. The CPU clocks will always be stopped in a low state and started in such a manner as to guarantee
that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time and CPU
clock off latency needs to be 2 or 3 CPU clocks periods in time.
CPU
CS#
CPU STOP TIMING
CPU
PCI
REF
48M
PD#
POWER DOWN TIMING
PCI
PS#
PCI STOP TIMING
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