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參數(shù)資料
| 型號： | C9914BY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 131K |
| 代理商： | C9914BY |
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07069 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 2 of 14
http://www.cypress.com
PRELIMINARY
C9914
Pin Description
PIN No.
Pin Name
PWR
I/O
Description
2
XIN
VDD
I
On-chip reference oscillator input pin. Requires either an external parallel
resonant crystal (nominally 14.318 MHz) or externally generated
reference signal
3
XOUT
VDD
O
O-chip reference oscillator output pin. Drives an external parallel
resonant crystal (14.318 MHz) when an externally generated reference
signal is used.
19
VDD
-
P
3.3 volt power supply for core logic.
23, 24
CPU(2,1)
VDDC
O
CPU Clock outputs. See frequency table page 1.
17
PD#
-
I
Powers down device when LOW
(1)
18
CS#
-
I
When signal is LOW, stops CPU clocks in low state.
(1)
16
SEL100/66#
-
I
Frequency select input pins. See frequency select table 1 on page 1. NO
INTERNAL PULLUP RESISTOR AT THIS INPUT.
25
VDDC
-
P
2.5V power for CPU and Host clock outputs.
4
PCI_F
VDDP
O
Free running PCI clock 3.3V. Does not stop when PS# is at a logic LOW
level
5,6,9,
10,11
PCI(1:5)
VDDP
O
PCI output clocks. See frequency table of page 1.
20
PS#
-
I
When signal is LOW, stops all PCI clocks in low state.
(1)
8
VDDP
-
P
3.3 Volt power supply pins for free running PCI clock output buffer.
13
48M
VDDF
O
Fixed 48 MHz clock.
14
48-24MHZ /
HFS#
VDDF
I/O
This is a Power up Bi-directional pin. During power up, this pin is an
HFS# input. HFS# is a High Frequency Select line for programming the
CPU/PCI output clock frequency, see table 1 page 1. For strapping
resistor, see application note page 5. When the power reaches the rail,
this pin becomes an SIO or USB clock output depending on the state of
pin 27, SEL48#. If SEL48# is strapped high, then the frequency is
24MHz, SIO. If SEL48# is strapped low, then the frequency is 48MHz,
USB.
(1)
26
REF1 / SS#
VDDR
I/O
At power up this pin determines if the device’s spread spectrum
modulation feature is enabled or disabled. After power up this pin
becomes a reference clock output. A 0 (logic low) enables SSCG and a 1
(logic high) disables SSCG.
(1)
27
REF2 /
SEL48#
VDDR
I/O
At power up this pin determine the frequency of the clock at pin 14. If it is
LOW, the clock will be 48 MHz, if HIGH the clock will be 24 MHz. After
power up this pin will become a reference clock output. (Default high)
12
VDDF
-
P
Power for fixed clock output buffer.
1,7,15,
21,22
VSS
-
P
Ground pins for device.
28
VDDR
-
P
Power for Reference Oscillator output buffer.
Note:
1.
Pins have internal pullup resistors that will guarantee to a logic 1 (high) level if no connection is made to the device’s pin. Other pins do not
contain this function and must be electrically connected to VDD or VSS by external circuitry to ensure a valid logic 1 or 0 is sensed.
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