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參數(shù)資料
| 型號： | C9815DY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 328K |
| 代理商： | C9815DY |
Low EMI Clock Generator for Intel
133MHz/2DIMM Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07054 Rev. **
05/03/2001
Page 2 of 19
APPROVED PRODUCT
C9815
Pin Description
PIN No.
1
Pin Name
SEL2/REF
PWR
VDD
I/O
I/O
Description
This is a bi-directional pin (see app. note, p.5). At power up, it is an input pin
Sel2 for selecting the CPU/SDRAM frequencies (see table 1 p.1). When the
power reaches the rail, the state of Sel2 is latched, and this pin becomes REF, a
buffer output of the signal applied at Xin, typically 14.318MHz. This pin has an
Internal Pull-Down. Typical 50K
(range 20K
to 70K
)
On-chip reference oscillator input pin. Requires either an external parallel
resonant crystal (nominally 14.318 MHz) or externally generated reference signal
On-chip reference oscillator pin. Drives an external parallel resonant crystal.
When an externally generated reference signal is used at Xin, this pin remains
unconnected.
3.3V PCI clock outputs. They are Synchronous to CPU clocks. See fig.3, page4.
3
XIN
VDD
I
4
XOUT
VDD
O
12,13,15,
16,18,19, 20
7, 8, 9
25
26
28, 29
PCI0_ICH
PCI(1..6)
3V66(0:2)
USB
DOT
SEL(0,1)
VDD
O
VDD
VDD
VDD
VDD
O
O
O
I
3.3V Fixed 66.6 MHz clock outputs. See fig.3 page 4.
3.3V Fixed 48 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL inputs for logic selection. This pin has an Internal Pull-Up. Typical
250K
(range 200K
to 500K
)
Serial data input pin. Conforms to the SMBUS specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See SMBUS function
description, pp.6,7,8.
Serial clock input pin. Conforms to the SMBUS specification.
3.3V LVTTL compatible input. When held LOW, the device enters a power down
mode. See description page 3. This pin has an Internal Pull-Up. Typical 250K
(range 200K
to 500K
)
3.3V SDRAM feedback clock. See table1, p.1 for frequency selection. See fig.3,
page 4 for timing relationship.
3.3V SDRAM DIMM clocks. See table1, p.1 for frequency selection. See fig.3,
page 4 for timing relationship.
2.5V Host clock outputs. See table 1 p. 1 for frequency selection.
30
SDATA
VDD
I/O
31
32
SCLK
PD#
VDD
VDD
I
I
34
DCLK
VDD
O
36,37,39,40,
42,43,45, 46
49, 50, 52
SDRAM(7..0)
VDDS
O
CPU(2)_ITP,C
PU(1,0)
IOAPIC(1,0)
VDD
VDDC
O
54, 55
2,10, 11, 21,
27, 33
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
38, 44
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
VDDI
-
O
2.5V IOAPIC clock outputs. See fig.3 p.4 for timing relationship.
3.3V Common Power Supply
VDDA
VSSA
VDDC, VDDI
VSS
-
-
-
-
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply
’
s
Common Ground pins.
VDDS
-
3.3V power support for SDRAM clock output drivers.
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