參數(shù)資料
型號(hào): C9821GQ
英文描述: Up to 5A ULDO linear regulator
中文描述: 單時(shí)鐘驅(qū)動(dòng)器| SSOP封裝| 24針|塑料
文件頁(yè)數(shù): 1/18頁(yè)
文件大小: 121K
代理商: C9821GQ
Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 1 of 18
APPROVED PRODUCT
C9821
Product Features
High Speed Clock support - provides a 267 to
400MHz differential clock source for Direct
Rambus
memory systems for an 1.6 GbPS
data transfer rate
Synchronization Flexibility - provides signals to
synchronize the clock domains of the Rambus
Channel with an external system or processor
clock, provided by C9801, C9812, C9830,
C9840, C9850, C9851, and the C9853.
Power Management Support permits channel
clocks to be enabled and disabled as required
Supports Independent Channel Clocking
24 pin 150 mil SSOP Package
Supports Intel Architecture platforms
Block Diagram
PLL
Phase
Aligner
Test
Logic
REFCLK
MULT 0:1
PCLKM
SYNCLKN
S0:2
STOPB
CLK
CLKB
Output
Control
Logic
Figure: 1
Product Description
The C9821 is a Rambus
compliant DRCG clock
synchronizer. It contains a Phase Locked Loop that
provides complimentary Rambus
memory clocks.
Included in its functionality is the control logic to
phase and frequency synchronizing the device’s
output clocks with the system reference clock. Power
management logic is also provided for Mobile
application and green PC functionality. Also included
are separate power pins for each internal functional
block so as to minimize interaction of these sections
with each other and thus maximize the device
performance.
Pin Configuration
VddlR
Refclk
VddP
VssP
VssI
PclkM
SynClkN
VssC
VddC
VddlPD
StopB
PwrDnB
S0
S1
VddO
VssO
Clk
N/C
ClkB
VssO
VddO
Mult0
Mult1
S2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Figure: 2
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