<menuitem id="hu7bh"><label id="hu7bh"></label></menuitem>
  • <var id="hu7bh"><input id="hu7bh"></input></var>
    參數(shù)資料
    型號(hào): C8051F547-IM
    廠商: Silicon Laboratories Inc
    文件頁(yè)數(shù): 31/274頁(yè)
    文件大小: 0K
    描述: IC 8051 MCU 8K FLASH 24-QFN
    應(yīng)用說(shuō)明: LIN Bootloader AppNote
    產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
    標(biāo)準(zhǔn)包裝: 91
    系列: C8051F54x
    核心處理器: 8051
    芯體尺寸: 8-位
    速度: 50MHz
    連通性: SMBus(2 線/I²C),SPI,UART/USART
    外圍設(shè)備: POR,PWM,溫度傳感器,WDT
    輸入/輸出數(shù): 18
    程序存儲(chǔ)器容量: 8KB(8K x 8)
    程序存儲(chǔ)器類型: 閃存
    RAM 容量: 1.25K x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.25 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 18x12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 24-WFQFN 裸露焊盤
    包裝: 管件
    配用: 336-1672-ND - BOARD PROTOTYPE W/C8051F540
    336-1669-ND - KIT DEVELOPMENT FOR C8051F540
    其它名稱: 336-1682-5
    第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)
    C8051F54x
    126
    Rev. 1.1
    15. Power Management Modes
    The C8051F54x devices have three software programmable power management modes: Idle, Stop, and
    Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an
    enhanced power-saving mode implemented by the high-speed oscillator peripheral.
    Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
    all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
    stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
    pend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
    wake on events such as a Port Match or Comparator low output. Since clocks are running in Idle mode,
    power consumption is dependent upon the system clock frequency and the number of peripherals left in
    active mode before entering Idle. Stop mode and Suspend mode consume the least power because the
    majority of the device is shut down with no clocks active. SFR Definition 15.1 describes the Power Control
    Register (PCON) used to control the C8051F54x devices’ Stop and Idle power management modes. Sus-
    pend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 17.2).
    Although the C8051F54x has Idle, Stop, and Suspend modes available, more control over the device
    power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral
    can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or
    serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption
    considerably, at the expense of reduced functionality.
    15.1. Idle Mode
    Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
    soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
    their original data. All analog and digital peripherals can remain active during Idle mode.
    Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
    enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
    operation. The pending interrupt will be serviced and the next instruction to be executed after the return
    from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
    If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
    and begins program execution at address 0x0000.
    Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
    during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
    when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
    instruction that has two or more opcode bytes, for example:
    // in ‘C’:
    PCON |= 0x01;
    // set IDLE bit
    PCON = PCON;
    // ... followed by a 3-cycle dummy instruction
    ; in assembly:
    ORL PCON, #01h
    ; set IDLE bit
    MOV PCON, PCON
    ; ... followed by a 3-cycle dummy instruction
    If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
    nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
    of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
    software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
    vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
    nitely, waiting for an external stimulus to wake up the system. Refer to Section “16.6. PCA Watchdog Timer
    Reset” on page 133 for more information on the use and configuration of the WDT.
    相關(guān)PDF資料
    PDF描述
    R5F72167ADFA#V0 IC MCU 32BIT 1MB FLASH 176LQFP
    UX40A-MB-5P CONN PLUG MINI USB2.0 5POS
    LPC1311FHN33,551 IC MCU 32BIT 8KB FLASH 33HVQFN
    C8051F332-GM IC 8051 MCU 4KB FLASH 20QFN
    C8051F300-GM IC 8051 MCU 8K FLASH 11QFN
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    C8051F547-IMR 功能描述:8位微控制器 -MCU 50 MIPS 8 kB 1 kB SPI UART I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    C8051F550-IM 功能描述:8位微控制器 -MCU 50 MIPS 32 kB 2 kB CAN2 LIN2.1 SPI UART RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    C8051F550-IMR 功能描述:8位微控制器 -MCU 50 MIPS 32 kB 2 kB CAN2.0 LIN 2.1 SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    C8051F551-IM 功能描述:8位微控制器 -MCU 50 MIPS 32 kB 2 kB CAN2 SPI UART RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    C8051F551-IMR 功能描述:8位微控制器 -MCU 50 MIPS 32 kB 2 kB CAN2.0 SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT