Rev. 1.1
273
C8051F54x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
information.
Updated Figure 8.1 to indicate that Comparators are powered from VIO and not VDDA. Updated Table 10.1 with correct timing for all branch instructions, MOVC, and CPL A. Updated Table 14.1 to indicate behavior when performing a Flash operation in reserved space. when writing/erasing Flash.
Updated SFR Definition 14.3 (FLSCL) to include FLEWT bit definition. This bit must be set before writing or erasing Flash. Also updated
Table 6.5 to reflect new Flash Write and Erase timing.
voltages above VIO.
Updated “20. SMBus” to remove all hardware ACK features, including SMB0ADM and SMB0ADR SFRs.
Updated CP Register Definition 24.2 with proper Device ID.
Note:
All items from the C8051F54x Errata dated November 5th, 2009 are incorporated into this data sheet.
Revision 1.0 to Revision 1.1
new timing diagram when using CNVSTR pin.
conditions for the internal oscillator accuracy. The internal oscillator accuracy is dependent on the
operating voltage range.
diagram.
Updated SFR Definition 9.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and must be written to 1b.
byte page from 0x3900 to 0x3A00.
oscillator.
Updated LIN Register Definitions for LIN0MUL and LIN0DIV to correct the reset value.
Updated C2 Register Definitions 25.2 and 25.3 with correct C2 and SFR addresses.