Page 10
DS007-0.4-NOV02
2002 Cygnal Integrated Products, Inc.
Advanced
Information
C8051F060/1/2/3
A
Figure 7.15. ADC Window Compare Example: Right-Justified Single-Ended Data..............95
Figure 7.16. ADC Window Compare Example: Left-Justified Single-Ended Data................95
Figure 7.17. ADC Window Compare Example: Right-Justified Differential Data.................96
Figure 7.18. ADC Window Compare Example: Left-Justified Differential Data...................96
Figure 5.23. ADC0CCF: ADC Calibration Coefficient Register............................................63Figure 5.24. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................64
Figure 5.25. ADC0GTL: ADC0 Greater-Than Data Low Byte Register................................64
Figure 5.26. ADC0LTH: ADC0 Less-Than Data High Byte Register....................................65
Figure 5.27. ADC0LTL: ADC0 Less-Than Data Low Byte Register.....................................65
Figure 5.28. 16-Bit ADC0 Window Interrupt Example: Single-Ended Data..........................66
Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data.............................67
6. DIRECT MEMORY ACCESS INTERFACE (DMA0).....................................................71
Figure 6.1. DMA0 Block Diagram........................................................................................71
Figure 6.2. DMA Mode 0 Operation .....................................................................................73
Figure 6.3. DMA Mode 1 Operation .....................................................................................74
Figure 6.4. DMA0CN: DMA0 Control Register...................................................................76
Figure 6.5. DMA0CF: DMA0 Configuration Register..........................................................77
Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register .....................................78
Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register..........................................78
Figure 6.8. DMA0BND: DMA0 Instruction Boundary Register ..........................................79
Figure 6.9. DMA0ISW: DMA0 Instruction Status Register..................................................79
Figure 6.10. DMA0DAH: DMA0 Data Address Beginning MSB Register ...........................80
Figure 6.11. DMA0DAL: DMA0 Data Address Beginning LSB Register.............................80
Figure 6.12. DMA0DSH: DMA0 Data Address Pointer MSB Register.................................80
Figure 6.13. DMA0DSL: DMA0 Data Address Pointer LSB Register...................................80
Figure 6.14. DMA0CTH: DMA0 Repeat Counter Limit MSB Register.................................81
Figure 6.15. DMA0CTL: DMA0 Repeat Counter Limit LSB Register..................................81
Figure 6.16. DMA0CSH: DMA0 Repeat Counter MSB Register...........................................81
Figure 6.17. DMA0CSL: DMA0 Repeat Counter LSB Register............................................81
7. 10-BIT ADC (ADC2).............................................................................................................83
Figure 7.1. ADC2 Functional Block Diagram.......................................................................83
Figure 7.2. Typical Temperature Sensor Transfer Function..................................................85
Figure 7.3. 10-Bit ADC Track and Conversion Example Timing.........................................86
Figure 7.4. ADC2 Equivalent Input Circuits.........................................................................87
Figure 7.5. AMX2CF: AMUX2 Configuration Register.......................................................88
Figure 7.6. AMX2SL: AMUX2 Channel Select Register.....................................................89
Figure 7.7. ADC2CF: ADC2 Configuration Register ...........................................................90
Figure 7.8. ADC2H: ADC2 Data Word MSB Register.........................................................91
Figure 7.9. ADC2L: ADC2 Data Word LSB Register..........................................................91
Figure 7.11. ADC2GTH: ADC2 Greater-Than Data High Byte Register...............................93
Figure 7.12. ADC2GTL: ADC2 Greater-Than Data Low Byte Register................................93
Figure 7.13. ADC2LTH: ADC2 Less-Than Data High Byte Register....................................94