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參數(shù)資料
| 型號： | BX805565130P |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封裝： | LGA-771 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 200K |
| 代理商： | BX805565130P |
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Dual-Core Intel Xeon Processor 5100 Series Specification Update
29
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG55.
Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem:
Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing with
the memory types WB and WT may cause the processor to perform incorrect operations
leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG56.
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem:
Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown (as
defined by the 4 step procedure in "Propagation of Page Table and Page Directory Entry
Changes to Multiple Processors" In volume 3A of the IA-32 Intel Architecture
Software Developer's Manual), in conjunction with a complex sequence of internal
processor micro-architectural events, may lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior.
Intel has not observed this erratum with any commercially available system.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG57.
BTS Message May Be Lost When the STPCLK# Signal is Active.
Problem:
STPCLK# is asserted to enable the processor to enter a low-power state. Under some
circumstances, when STPCLK# becomes active, the BTS (Branch Trace Store) message
may be either lost and not written or written with corrupted branch address to the
Debug Store area
Implication: BTS messages may be lost or be corrupted in the presence of STPCLK# assertions.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG58.
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
to 248 May Terminate Early
Problem:
In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count
greater than or equal to 248 may terminate early. Early termination may result in one of
the following:
The last iteration not being executed
Signaling of a canonical limit fault (#GP) on the last iteration
Implication: While in 64-bit mode, with count greater or equal to 248, repeat string operations
CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel
has not observed this erratum with any commercially available software.
Workaround: Do not use repeated string operations with RCX greater than or equal to 248.
Status:
For the steppings affected, see the Summary Tables of Changes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX805565140P S LABN | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565148A S LABH | 制造商:Intel 功能描述:MPU Xeon |
| BX805565160A S L9RT | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160A S LABS | 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box |
| BX805565160P S LAG9 | 制造商:Intel 功能描述: |
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