參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁數(shù)： 10/40頁
文件大小： 200K
代理商： BX805565130P
18
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AG13.
Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May be Incorrect
Problem:
Performance-Monitoring Counter PMH_PAGE_WALK is used to count the number of
page walks resulting from Data Translation Look-Aside Buffer (DTLB) and Instruction
Translation Look-Aside (ITLB) misses. Under certain conditions, this counter may be
incorrect.
Implication: There may be small errors in the accuracy of the counter.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG14.
Last Exception Record (LER) MSRs May be Incorrectly Updated
Problem:
The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect
values after the following events: StopClk, NMI and INT.
Implication: The value of the LER MSR may be incorrectly updated to point to an instruction that
was preceded by a StopClk interrupt or rarely not to be updated on Interrupts (NMI and
INT).
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG15.
Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
Problem:
The INST_RETIRED performance monitor may miscount retired instructions as follows:
Repeat string and repeat I/O operations are not counted when a hardware interrupt
is received during or after the last iteration of the repeat flow.
VMLAUNCH and VMRESUME instructions are not counted.
HLT and MWAIT instructions are not counted. The following instructions, if executed
during HLT or MWAIT events, are also not counted:
— a) RSM from a C-state SMI during an MWAIT instruction.
— b) RSM from an SMI during a HLT instruction.
Implication: There may be a smaller than expected value in the INST_RETIRED performance
monitoring counter. The extent to which this value is smaller than expected is
determined by the frequency of the above cases.
Workaround: None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG16.
Performance Monitoring Event For Number Of Reference Cycles When
The Processor Is Not Halted (3CH) Does Not Count According To The
Specification
Problem:
The CPU_CLK_UNHALTED performance monitor with mask 1 counts bus clock cycles
instead of counting the core clock cycles at the maximum possible ratio. The maximum
possible ratio is computed by dividing the maximum possible core frequency by the bus
frequency.
Implication: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than
expected. The value is lower by exactly one multiple of the maximum possible ratio.
Workaround: Multiply the performance monitor value by the maximum possible ratio.
Status:
For the steppings affected, see the Summary Tables of Changes.
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參數(shù)描述
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BX805565160P S LAG9 制造商:Intel 功能描述:
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