參數(shù)資料
型號(hào)： BX805565130P
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, MICROPROCESSOR, BGA771
封裝： LGA-771
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 200K
代理商： BX805565130P
24
Dual-Core Intel Xeon Processor 5100 Series Specification Update
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel Architecture
Software Developer's Manual Volume 3: System Programming Guide, including a
General Protection Fault (GPF) or other unexpected behaviors. In the event that
unpredictable execution causes a GPF the application executing the unsynchronized
XMC operation would be terminated by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC synchronization
algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3:
System Programming Guide, Section: Handling Self- and Cross-Modifying Code.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG34.
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
Problem:
When an MCE occurs during execution of a RDMSR instruction for MSRs Actual
Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count
(IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may
contain incorrect data.
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return
incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG35.
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
Problem:
A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG36.
Split Locked Stores May not Trigger the Monitoring Hardware
Problem:
Logical processors normally resume program execution following the MWAIT, when
another logical processor performs a write access to a WB cacheable address within the
address range used to perform the MONITOR operation. Due to this erratum, a logical
processor may not resume execution until the next targeted interrupt event or O/S
timer tick following a locked store that spans across cache lines within the monitored
address range.
Implication: The logical processor that executed the MWAIT instruction may not resume execution
until the next targeted interrupt event or O/S timer tick in the case where the
monitored address is written by a locked store which is split across cache lines.
Workaround: Do not use locked stores that span cache lines in the monitored address range.
Status:
For the steppings affected, see the Summary Tables of Changes.
AG37.
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when
RCX >= 0X100000000
Problem:
REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit mode may
terminate before the count in RCX reaches zero if the initial value of RCX is greater
than or equal to 0X100000000.
相關(guān)PDF資料
PDF描述
BX805573060 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775
BX80562X3210SLACU 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775
BX80616I5660SLBLV 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156
BXA10-48D15-S DC to DC Converter
BXA10-48S05 EMI FILTER INCLUDING ESD PROTECTION
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX805565140P S LABN 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5140 RISC 64-Bit 65nm 2.33GHz 1.35V/1.5V 771-Pin FCLGA6 Box
BX805565148A S LABH 制造商:Intel 功能描述:MPU Xeon
BX805565160A S L9RT 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box
BX805565160A S LABS 制造商:Intel 功能描述:MPU Xeon? Processor 5160 RISC 64-Bit 65nm 3GHz 1.35V/1.5V 771-Pin FCLGA6 Box
BX805565160P S LAG9 制造商:Intel 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*