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參數(shù)資料
| 型號： | BX80552661 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 3600 MHz, MICROPROCESSOR, PBGA775 |
| 封裝： | FLIP CHIP, LGA-775 |
| 文件頁數(shù)： | 97/108頁 |
| 文件大?。?/td> | 3283K |
| 代理商： | BX80552661 |
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Datasheet
91
Features
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the logical processors have executed the HALT or
MWAIT instructions. When one of the logical processors executes the HALT instruction, that
logical processor is halted; however, the other processor continues normal operation. The processor
will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]
(NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:
System Programmer's Guide for more information.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When
the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT
state.
While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2
Enhanced HALT Powerdown State
Enhanced HALT is a low power state entered when all logical processors have executed the HALT
or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the
logical processors executes the HALT instruction, that logical processor is halted; however, the
other processor continues normal operation.
The processor will automatically transition to a lower frequency and voltage operating point before
entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the
internal core frequency is changed. When entering the low power state, the processor will first
switch to the lower bus ratio and then transition to the lower VID.
While in Enhanced HALT state, the processor will process bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the processor exits
the Enhanced HALT state, it will first transition the VID to the original value and then change the
bus ratio back to the original value.
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PDF描述 |
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| BX80552651T2 | 32-BIT, 3400 MHz, MICROPROCESSOR, PBGA775 |
| BX80552641T | 32-BIT, 3200 MHz, MICROPROCESSOR, PBGA775 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80552661T2 | 制造商:Intel 功能描述:P4 661 3.6GHZ LP-BTX 2MB - Boxed Product (Development Kits) |
| BX80553915 S L9KB | 制造商:Intel 功能描述: |
| BX80553915R S L9DA | 制造商:Intel 功能描述: |
| BX80553925 S L9KA | 制造商:Intel 功能描述: |
| BX80553945 S L9QQ | 制造商:Intel 功能描述:PENTIUM D PROCESSOR 945 |
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