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參數(shù)資料
| 型號： | BX80532KE3066E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3060 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 81/102頁 |
| 文件大小： | 1464K |
| 代理商： | BX80532KE3066E |
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8
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
mPGA package. This additional pin serves as a keying mechanism to prevent the FC-mPGA2
package from being installed in the 603-pin socket since processors in the FC-mPGA2 package are
only supported in the 604-pin socket. Since the additional contact for pin AE30 is electrically inert,
the 604-pin socket will not have a solder ball at this location.
Mechanical components used for attaching thermal solutions to the baseboard should have a high
degree of commonality with the thermal solution components enabled for the Intel Xeon processor
Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.
Hence, mechanical assembly can be completed from the top of the baseboard.
The Intel Xeon processor with 533 MHz Front Side Bus uses a scalable front side bus protocol
referred to as the “Front Side Bus” in this document. The processor front side bus utilizes a split-
transaction, deferred reply protocol similar to that introduced by the Pentium Pro processor Front
Side Bus, but is not compatible with the Pentium Pro processor front side bus. The Intel Xeon
processor with 533 MHz Front Side Bus is compatible with the Intel Xeon processor Front Side
Bus. The front side bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4.3
Gigabytes per second. Finally, the front side bus also introduces transactions that are used to
deliver interrupts.
Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described
in the appropriate platform design guide (refer to Section 1.3).
NOTE:
1. Refers to The Intel Xeon Processor with 1-MB and 2-MB L3 cache at 3.06 and 3.20 GHz.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Front Side Bus (FSB): The electrical interface that connects the processor to the chipset. Also
referred to as the processor system bus or the system bus. All memory and I/O transactions as well
as interrupt messages pass between the processor and chipset over the FSB.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
604-pin socket - The 604-pin socket contains an additional contact to accept the additional
keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The
604-pin socket will also accept processors with the INT-mPGA package. Since the additional
contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this
location. Therefore, the additional keying pin will not require a baseboard via nor a surface-
mount pad. See the mPGA604 Socket Design Guidelines for details regarding this socket.
相關PDF資料 |
PDF描述 |
|---|---|
| BX80532RC2400B | 32-BIT, 2400 MHz, MICROPROCESSOR |
| BU-61559D1-230W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D1-230 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D1-260Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D1-340Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KE3066EU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 3.06GHZ - Boxed Product (Development Kits) |
| BX80532KE3200F | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 3.2GHZ - Boxed Product (Development Kits) |
| BX80532PC1800D | 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 1.8GHZ - Boxed Product (Development Kits) |
| BX80532PC2000D | 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) 制造商:Intel 功能描述:P4 Socket 478 2.0GHz with fan |
| BX80532PC2200D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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