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參數(shù)資料
| 型號(hào)： | BX80523R266000 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁(yè)數(shù)： | 25/130頁(yè) |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80523R266000 |
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120
Datasheet
Intel Celeron Processor up to 1.10 GHz
7.0
Processor Signal Description
Table 59 provides an alphabetical listing of all Celeron processor signals. The tables at the end of
this section summarize the signals by direction (output, input, and I/O).
Note:
Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA/FC-PGA2 Packages.
Table 59. Alphabetical Signal Reference (Sheet 1 of 7)
Signal
Type
Description
A[31:3]#
I/O
The A[31:3]# (Address) signals define a 232-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the Intel
Celeron processor system
bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the
A[23:3]# signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]#
pins to determine their power-on configuration. See the Pentium II Processor
Developer’s Manual
(Order Number 243502) for details.
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron
processor masks physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[31:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system
bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron
processor system bus agents must receive this signal to drive their outputs and latch
their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BNR#
I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all Intel Celeron
processor system bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BNR# is activated on
specific clock edges and sampled on specific clock edges.
BP[3:2]#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BPM[1:0]#
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BUS-61565-100 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, DFP82 |
| BU-61580V6-120 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61581V0-300 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61586V3-150 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61580S0-140 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
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