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參數(shù)資料
| 型號： | BW1218L |
| 英文描述： | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1218L 10位5?高達10MSPS模數(shù)轉換器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1218L |
BW1217X
10BIT 30MSPS ADC
SEC ASIC
ANALOG
TIMING
DIAGRAM( Main Function )
track
hold
track
hold
track
hold
track
hold
track
hold
ref sample
amplify
precharge
latch
track
latch
encoding
input
sample
residue
amplify
input
sample
residue
amplify
ref sample
latch
track
latch
encoding
amplify
precharge
input
sample
residue
amplify
input
sample
residue
amplify
ref sample
latch
track
amplify
precharge
DATA
AIN
CLOCK
SHA
MDAC1
FLASH1
FLASH2
MDAC2
FLASH3
DATA
latch
encoding
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| BW1219A | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| BW1219B | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| BW1223X | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1224L | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1227L | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
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| BW1221L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L 10Bit 80MSPS Dual DAC BW1221L|Data Sheet |
| BW1221L_2CLK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L_2CLK 10BIT|Data Sheet |
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