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參數(shù)資料
| 型號： | BW1218L |
| 英文描述： | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1218L 10位5?高達(dá)10MSPS模數(shù)轉(zhuǎn)換器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 140K |
| 代理商： | BW1218L |
BW1217X
10BIT 30MSPS ADC
SEC ASIC
ANALOG
CORE
PIN
DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
AINT
AI
piar50_bb
Analog Input +
(Input Range : 0.5V ~ 2.5V)
AINC
AI
piar50_bb
Analog Input : (DC=1.5V)
REFMID
AB
pia_bb
Reference Mid Point (Test Pin)
REFTOP
AI
pia_bb
Reference Top (2.0V)
REFBOT
AI
pia_bb
Reference Bottom(1.0V)
VDDA
AP
vdda
Analog Power ( 3.3V )
VSSA
AG
vssa
Analog Ground
VBBA
AG
vbba
Analog Sub Bias
ITEST
AB
pia_bb
open=use internal bias point
STBY
DI
picc_bb
high=power saving standby mode
(normally = gnd)
CKIN
DI
picc_bb
Sampling Clock Input
CML
AB
pia_bb
Internal Bias Point(Test Pin)
DO[9:0]
DO
pot2_bb
Digital Output
OVF
DO
pot2_bb
Overflow
UDF
DO
pot2_bb
Underflow
VBBD
DG
vbba
Digital Sub Bias
VSSD
DG
vssd
Digital Ground
VDDD
DP
vddd
Digital Power
CORE
CONFIGURATION
bw1217x
AINT
ITEST
REFMID
CML
AINC
REFTOP
REFBOT
CKIN
DO[9:0]
STBY
I/O TYPE ABBR.
- AI : Analog Input
- DI : Digital Input
- AO : Analog Output
- DO : Digital Output
- AB : Analog Bidirectional
- DB : Digital Bidirectional
- AP : Analog Power
- DP : Digital Power
- AG : Analog Ground
- DG : Digital Ground
VDDA
VSSA
VBBA
VDDD
VSSD
VBBD
UDF
OVF
2 / 11
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| BW1219A | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
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| BW1223X | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
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| BW1227L | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
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