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參數(shù)資料
| 型號(hào)： | BW1218L |
| 英文描述： | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1218L 10位5?高達(dá)10MSPS模數(shù)轉(zhuǎn)換器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 140K |
| 代理商： | BW1218L |
BW1217X
10BIT 30MSPS ADC
SEC ASIC
ANALOG
USER GUIDE
1. Resolution Control.
- Modular structure is the most important feature of BW1217X.
- You can get any resolution you want by combining each primary module (MDAC + FLASH) without major
circuit change.
- It means you don't have to redesign the most difficult analog block for another resolution.
- But this simple resolution control method has a limit up to 10bits, otherwise the internal op-amp must be
redesigned.
2. Speed Up
- The initial target speed of BW1217X was 30MHz, but it proved to operate well at 35MHz or more
due to a lot of design margin.
3. Input Range Variation.
- The default of the input of this ADC is differential -1.0V ~ +1.0V.
- The bias voltages of both AINT and AINC are 0.5V~2.5V, and their offset is 1.5V.
- In order to change to another input voltage range, alter the voltage values of AINT and AINC after setting
Reftop and Refbot to the maximum value of input range.
- If you want single ended input, fix AINC to 1.5V as a ground and the internal input voltage level is
V(aint)-1.5V.
4. Verilog Modeling
- Verilog modeling needs 64bits for only one analog real signal.
ain
sha
mdac1
mdac2
flash1
flash2
flash3
dclogic
10bit
module
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相關(guān)PDF資料 |
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| BW1219A | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| BW1219B | Low voltage CMOS 16-bit bus buffer (3-state inverter) with 3.6 V tolerant inputs and outputs |
| BW1223X | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1224L | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1227L | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
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