參數(shù)資料
型號: BUK107-50DS
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: PowerMOS transistor Logic level TOPFET(功率MOS晶體管邏輯電平TOPEFT)
中文描述: 0.7 A, 50 V, 0.175 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁數(shù): 3/9頁
文件大?。?/td> 75K
代理商: BUK107-50DS
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DS
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Thermal resistance
Junction to solder point
Junction to board
1
Junction to ambient
R
th j-sp
R
th j-b
R
th j-a
-
-
-
12
40
-
18
-
70
K/W
K/W
K/W
Mounted on any PCB
Mounted on PCB of fig. 19
STATIC CHARACTERISTICS
T
b
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(CL)DSS
V
(CL)DSS
Drain-source clamping voltage
Drain-source clamping voltage
V
IS
= 0 V; I
D
= 10 mA
V
IS
= 0 V; I
DM
= 200 mA;
t
p
300
μ
s;
δ
0.01
V
DS
= 45 V; V
IS
= 0 V
V
DS
= 50 V; V
IS
= 0 V
V
DS
= 40 V; V
IS
= 0 V; T
j
= 100 C
I
I
= 1.5 mA; I
DM
= 100 mA;
t
p
300
μ
s;
δ
0.01
50
-
55
56
-
V
V
70
I
DSS
I
DSS
I
DSS
R
DS(ON)
Off-state drain current
Off-state drain current
Off-state drain current
Drain-source on-state
resistance
2
-
-
-
-
0.5
1
10
125
2
20
100
175
μ
A
μ
A
μ
A
m
INPUT CHARACTERISTICS
T
b
= 25 C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
The input clamping is suitable for a drive circuit with a pull-up resistor.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
I
IS
I
ISL
Input threshold voltage
Input supply current
Input supply current
V
DS
= 5 V; I
D
= 1 mA
normal operation;
protection latched;
1.7
-
-
-
1
6
-
2.2
550
500
250
2.2
7.5
33
2.7
750
650
400
3.5
-
-
V
μ
A
μ
A
μ
A
V
V
k
V
IS
= 6 V
V
IS
= 5 V
V
IS
= 3.5 V
V
ISR
V
(CL)IS
R
IG
Protection latch reset voltage
3
Input clamping voltage
Input series resistance
I
I
= 1.5 mA
to gate of power MOSFET
SWITCHING CHARACTERISTICS
T
amb
= 25 C; resistive load R
L
= 50
; adjust V
DD
to obtain I
D
= 250 mA; refer to test circuit and waveforms
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
d on
t
r
t
d off
t
f
Turn-on delay time
V
IS
= 0 V to I
I
= 1.5 mA
-
4
-
μ
s
μ
s
μ
s
μ
s
Rise time
-
16
-
Turn-off delay time
I
I
= 1.5 mA to V
IS
= 0 V
-
3
-
Fall time
-
6
-
1
Temperature measured 1.3 mm from tab.
2
Continuous input voltage. The specified pulse width is for the drain current.
3
The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
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