參數(shù)資料
型號: BU52021HFV
元件分類: Magnetic Field Sensor
英文描述: MAGNETIC FIELD SENSOR-HALL EFFECT, 0.8-5.5mT, 0.40-2.60V, RECTANGULAR, SURFACE MOUNT
封裝: VSOF-5
文件頁數(shù): 9/11頁
文件大?。?/td> 2025K
代理商: BU52021HFV
7/11
BU52015GUL
Fig.21
Description of Operation
(Ultra-low Power Operation)
(Offset Cancellation)
Pin.No
Pin
Description
Remarks
A1
OUT1
Output pin (Active Low)
A2
OUT2
Output pin (Active High)
D
N
U
O
R
G
D
N
G
1
B
B2
VDD
Power supply
GND
OUT1
OUT2
LA
TCH
VDD
GND
VDD
TIMING LOGIC
S
A
M
P
LE
&
H
O
LD
HALL
ELEMENT
DYNAMIC O
FFSE
T
CANCELL
ATION
A1
A2
B1
B2
The bipolar detection Hall IC utilizes an intermittent
operation method to save energy. At startup, the Hall
elements, amp, comparator and other detection circuits
power ON and magnetic detection begins. During standby,
the detection circuits power OFF, reducing current
consumption. The detection results are held while standby
is active, and then output.
Reference period: 50ms (100ms Max.)
Reference startup time: 48 s
IDD
Standby
Startup time
Period
t
Fig.22
The Hall elements form an equivalent Wheatstone (resistor)
bridge circuit. Offset voltage may be generated by a
differential in this bridge resistance, or can arise from
changes in resistance due to package or bonding stress. A
dynamic offset cancellation circuit is employed to cancel this
offset voltage.
When Hall elements are connected as shown in Fig. 23 and a
magnetic field is applied perpendicular to the Hall elements
voltage is generated at the mid-point terminal of the bridge.
This is known as Hall voltage.
Dynamic cancellation switches the wiring (shown in the
figure) to redirect the current flow to a 90 angle from its
original path, cancelling the Hall voltage.
The magnetic signal (only) is maintained in the sample/hold
circuit during the offset cancellation process, then
released
GND
VDD
I
B
Hall Voltage
Fig.23
0.1 F
The CMOS output terminals enable direct
connection to the PC with no external pull-up
resistor required.
Adjust the bypass capacitor
value as necessary, based on
voltage noise conditions, etc.
A1
B2
B1
A2
Bottom
A2
B2
B1
A1
Top
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