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參數(shù)資料
| 型號： | BU-65863F3-220 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件頁數(shù)： | 67/75頁 |
| 文件大小： | 532K |
| 代理商： | BU-65863F3-220 |
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Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
The PCI Mini-ACE Mark3/Micro-ACE TE RT offers the same
choices of single and circular buffering for individual subad-
dresses as ACE, Mini-ACE(Plus), and Enhanced Mini-ACE. New
enhancements to the RT architecture include a global circular
buffering option for multiple (or all) receive subaddresses, a 50%
rollover interrupt for circular buffers, an interrupt status queue for
logging up to 32 interrupt events, and an option to automatically
initialize to RT mode with the Busy bit set. The interrupt status
queue and 50% rollover interrupt features are also included as
improvements to the PCI Mini-ACE Mark3/Micro-ACE TE's
Monitor architecture.
The PCI Mini-ACE Mark3 series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL PRF-38534C, the terminals are ideal for military and
industrial processor to 1553 applications.
The PCI Micro-ACE TE terminals operate over an extended tem-
perature range of -40°C to +100°C.
TRANSCEIVERS
The transceivers in the PCI Mini-ACE Mark3 series terminals are
fully monolithic, requiring only a +3.3V power input or a +5V
power input. The transmitters are voltage sources, which provide
improved line driving capability over current sources. This serves
to improve performance on long buses with many taps. The
transmitters also offer an option which satisfies the MIL-STD-
1760 requirement for a minimum of 20 volts peak-to-peak, trans-
former coupled output. The transceivers in the PCI Micro-ACE
TE are only available with the MIL-STD-1760 option.
Besides eliminating the demand for an additional power supply,
the use of a +3.3V only or +5V only transceiver requires the use
of a step-up, rather than a step-down, isolation transformer. This
provides the advantage of higher terminal input impedance than
is possible for a 15 volt or 12 volt transmitter. As a result, there is
a greater margin for the input impedance test, mandated for the
1553 validation test. This characteristic allows for longer cable
lengths between a system connector and the isolation trans-
formers of an embedded 1553 terminal.
To provide compatibility to McAir specs, the PCI Mini-ACE Mark3
is available with an option for transmitters with increased rise and
fall times.
All PCI Micro-ACE TE parts can be operated with external trans-
ceivers. This is achieved by bonding out the required protocol
and transceiver I/O pads to BGA balls. Most applications will use
the internal transceivers, which requires PCB traces to intercon-
nect protocol output balls to transceiver input balls and trans-
ceiver output balls to protocol input balls. These interconnections
are listed in TABLE 71.
The 3.3V transceiver parts also have a SLEEP_IN input.
Asserting SLEEP_IN puts the transceivers into a power saving
mode during which the receiver and transmitter of the trans-
ceivers are disabled.
The receiver sections of the PCI Mini-ACE Mark3/Micro-ACE TE
are fully compliant with MIL-STD-1553B Notice 2 in terms of
front-end overvoltage protection, threshold, common mode
rejection, and word error rate.
PCI REGISTER AND MEMORY ADDRESS
The PCI Interface contains a set of "Type 00h" PCI configuration
registers that are used to map the device into the host system.
There are two Base Address Registers that are used to imple-
ment ACE memory space (BAR0) and register space (BAR1).
The PCI configuration register space is mapped in accordance
with PCI revision 2.2 specifications.
The PCI mini-ACE Mark3 acts as a target and responds to the
following PCI commands:
1111 (Fh)
MEMORY WRITE & INVALIDATE
1110 (Eh)
MEMORY READ LINE
1100 (Ch)
MEMORY READ MULTIPLE
1011 (Bh)
CONFIGURATION WRITE
1010 (Ah)
CONFIGURATION READ
0111 (7h)
MEMORY WRITE
0110 (6h)
MEMORY READ
CODE (C/BE[3:0]#)
COMMAND TYPE
TABLE 2. PCI TARGET COMMAND CODES
The PCI mini-ACE Mark3 does NOT implement the Memory
Read Multiple, Memory Read Line or Memory Write and
Invalidate commands. However, in accordance with PCI rules,
the PCI mini-ACE Mark3 will accept these requests and alias
them to the basic memory commands. For example, Memory
Read Multiple and Memory Read Line commands will be accept-
ed and treated as Memory Read commands. Similarly, the PCI
mini-ACE Mark3 will accept a memory Write and Invalidate com-
mand and treat it as a Memory Write command.
ACE memory is accessed internally in 16-bit words, but memory
is accessed sequentially allowing for 32-bits of data to be read
from the PCI bus. In other words, if a 32-bit PCI read is request-
ed the first 16 bits of data would be read from the requested
internal address, the next 16 bits of data would be read from the
initial internal address + 1, and then the resulting 32-bit double
word would be transferred to the PCI bus. The PCI Mini-ACE
Mark3 supports 32-bit and 16-bit read and write operations, 8 bit
reads will return 16 bit data, and 8 bit writes are illegal and will
cause target-aborts.
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