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參數(shù)資料
| 型號(hào)： | BU-65863F3-220 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件頁數(shù)： | 24/75頁 |
| 文件大小： | 532K |
| 代理商： | BU-65863F3-220 |
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Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
General Purpose Queue. The PCI Mini-ACE Mark3/Micro-ACE
TE BC allows for the creation of a general purpose queue. This
data structure provides a means for the message sequence
processor to convey information to the BC host. The BC op
code repertoire provides mechanisms to push various items on
this queue. These include the contents of the Time Tag
Register, the Block Status Word for the most recent message,
an immediate data value, or the contents of a specified memo-
ry address.
FIGURE 5 illustrates the operation of the BC General Purpose
Queue. Note that the BC General Purpose Queue Pointer
Register will always point to the next address location (modulo
64); that is, the location following the last location written by the
BC message sequence control engine.
If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER
interrupt will be issued when the value of the queue pointer
address rolls over at a 64-word boundary. The rollover will always
occur at a modulo 64 address.
REMOTE TERMINAL (RT) ARCHITECTURE
The PCI Mini-ACE Mark3/Micro-ACE TE's RT architecture builds
upon that of the ACE and Mini-ACE. The PCI Mini-ACE
Mark3/Micro-ACE TE provides multiprotocol support, with full
compliance to all of the commonly used data bus standards,
including MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG
3838, General Dynamics 16PP303, and McAirA3818, A5232,
and A5690. For the PCI Mini-ACE Mark3/Micro-ACE TE RT
mode, there is programmable flexibility enabling the RT to be con-
figured to fulfill any set of system requirements. This includes the
capability to meet the MIL-STD-1553A response time require-
ment of 2 to 5 s, and multiple options for mode code subad-
dresses, mode codes, RT status word, and RT BIT word.
The PCI Mini-ACE Mark3/Micro-ACE TE RT protocol design
implements all of the MIL-STD-1553B message formats and dual
redundant mode codes. The design has passed validation testing
for MIL-STD-1553B compliance. The PCI Mini-ACE Mark3/Micro-
ACE TE RT performs comprehensive error checking including
word and format validation, and checks for various RT-to-RT
transfer errors. One of the main features of the PCI Mini-ACE
Mark3/Micro-ACE TE RT is its choice of memory management
options. These include single buffering by subaddress, double
buffering for individual receive subaddresses, circular buffering by
individual subaddresses, and global circular buffering for multiple
(or all) subaddresses.
Other features of the PCI Mini-ACE Mark3/Micro-ACE TE RT
include a set of interrupt conditions, an interrupt status queue with
filtering based on valid and/or invalid messages, internal com-
mand illegalization, programmable busy by subaddress, multiple
options on time tagging.
LAST LOCATION
BC GENERAL
PURPOSE QUEUE
(64 Locations)
BC GENERAL
PURPOSE QUEUE
POINTER
REGISTER
NEXT LOCATION
FIGURE 5. BC GENERAL PURPOSE QUEUE
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