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參數(shù)資料
| 型號： | BU-61843F4-192Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72 |
| 文件頁數(shù)： | 43/56頁 |
| 文件大?。?/td> | 321K |
| 代理商： | BU-61843F4-192Y |
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48
60
59
2
30
25
60
59
2
30
25
TX_INH_B (1)
TX_INH_A (1)
MSTCLR(1)
CLOCK_IN (1)
INCMD (O) /
MCRST (O)
INT (0)
UPADDREN
Transmitter inhibit inputs for the Channel A and Channel B MIL-STD-1553 transmitters.
For normal operation, these inputs should be connected to logic "0". To force a shutdown
of Channel A and/or Channel B, a value of logic "1" should be applied to the respective
TX_INH input.
Master Clear. Negative true Reset input, normally asserted low following power turn-on.
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
In-command or Mode Code Reset. The function of this pin is controlled by bit 0 of
Configuration Register #7, MODE CODE RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is being
processed by the Enhanced Mini-ACE. In Word Monitor mode, INCMD will be asserted
low for as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal
is inoperative; i.e., in this case, it will always output a value of logic "1".
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration
Register #2 is logic "0", a negative pulse of approximately 500ns in width is output on
INT to signal an interrupt request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT. The
level interrupt will be cleared (high) after either: (1) The processor writes a value of logic
"1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then it will
only be necessary to read the Interrupt Status Register (#1 and/or #2) that is requesting
an interrupt that has been enabled by the corresponding Interrupt Mask Register.
However, for the case where both Interrupt Status Register #1 and Interrupt Status
Register #2 have bits set reflecting interrupt events, it will be necessary to read both
interrupt status registers in order to clear INT.
For BU-61864/61865, this pin is +5V-RAM and MUST be connected to +5V.
For BU-61743(5) and 61843(5), this signal is used to control the function of the upper 4
address inputs (A15-A12). For these versions of Enhanced Mini-ACE, if UPADDREN is
connected to logic "1", then these four signals operate as address lines A15-A12.
For BU-61843(5)/61743(5), if UPADDREN is connected to logic "0", then A15 and A14
function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be connected to Vcc-
LOGIC (+5V or +3.3V); and A12 functions as RTBOOT.
PIN
BU-61843(5) /
61743(5)
(4KK RAM)
PIN
BU-61864(5)
(64K RAM)
MISCELLANEOUS
SIGNAL NAME
57
26
57
-
DESCRIPTION
For factory test only. Do not connect for normal operation.
XCVR_TP (ZAP VOLTB)
XCVR_TP (RESET)
P2(*)
P3(*)
P4(*)
XCVR_TP (READOUTB)
XCVR_TP (CLOCK)
XCVR_TP (READOUTA)
FACTORY TEST
XCVR_TP (ZAP VOLTA)
P1(*)
SIGNAL NAME
PIN
P6(*)
P5(*)
(*) Note that the Test Output pins are recessed pads located on the bottom of the package.
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相關(guān)代理商/技術(shù)參數(shù) |
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| BU-61843G3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| BU-61843G4-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61843G4-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61845 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
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