參數(shù)資料
型號(hào)： BU-61843F4-192Y
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72
文件頁(yè)數(shù)： 38/56頁(yè)
文件大小： 321K
代理商： BU-61843F4-192Y
43
PIN
SIGNAL NAME
PROCESSOR ADDRESS BUS
BU-61843(5) /
61743(5)
(4KK RAM)
DESCRIPTION
70
A12 / RTBOOT
71
A13 / Vcc -LOGIC
8
A14 / CLK_SEL_0
66
A15 / CLK_SEL_1
For BU-61864(5) (64K RAM version), this signal is always configured as address line A12. Refer
to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A12.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this
signal functions as RTBOOT. If RTBOOT is connected to logic "0", the Enhanced Mini-ACE will
initialize in RT mode with the Busy status word bit set following power turn-on. If RTBOOT hard-
wired to logic "1", the Enhanced Mini-ACE will initialize in either Idle mode (for an RT-only part), or
in BC mode (for a BC/RT/MT part).
A12
For BU-61864(5) (64K RAM version), this signal is always configured as address line A13. Refer
to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A13.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then
this signal MUST be connected to +5V/+3.3V-LOGIC (logic "1" ).
A13
For BU-61864(5) (64K RAM version), this signal is always configured as address line A14. Refer
to the description of A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A14.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this
signal operates as CLK_SEL_1. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Enhanced Mini-ACE's clock frequency, as defined in the description for A15/CLK_SEL1 above.
A14
For BU-61864(5) (64K RAM version), this signal is always configured as address line A15 (MSB).
Refer to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as address line A15.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", this signal
operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Enhanced Mini-ACE's clock frequency, as follows:
Clock
CLK_SEL_1
CLK_SEL_0
Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
A15
BU-61864(5)
(64K RAM)
相關(guān)PDF資料
PDF描述
BU-61843G3-140L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BC414P 100 mA, 45 V, NPN, Si, SMALL SIGNAL TRANSISTOR
BC414PSTOB 100 mA, 45 V, NPN, Si, SMALL SIGNAL TRANSISTOR
BC414PSTOA 100 mA, 45 V, NPN, Si, SMALL SIGNAL TRANSISTOR
BC415PSTOB 100 mA, 30 V, PNP, Si, SMALL SIGNAL TRANSISTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BU-61843G3-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61843G3-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61843G4-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61843G4-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61845 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE?
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