參數(shù)資料
型號: BU-61843F4-192Y
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72
文件頁數(shù): 29/56頁
文件大?。?/td> 321K
代理商: BU-61843F4-192Y
35
HOST
Enhanced
55
55
CH. A
TX/RXA
55
55
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V (3.3V)
(NOTE 5)
CLK IN
CLOCK
OSCILLATOR
N/C
POLARITY_SEL
(NOTE 2)
ZERO_WAIT
(NOTE 3)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
(NOTE 4)
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
NOTES:
3. ZERO_WAIT SHOULD BE STRAPPED TO
LOGIC "1" FOR NON-ZERO WAIT INTERFACE
AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY
FOR NON-ZERO WAIT TYPE OF INTERFACE.
5. +3.3V POWER FOR BU-61743 / 61843 / 61864 ONLY
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED
ADDRESS AND DATA BUSSES, ADDR_LAT SHOULD BE
CONNECTED TO +5V.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,
LOW TO WRITE.
IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,
HIGH TO WRITE.
A15-A12
A11-A0
N/C
ADDR_LAT
TRANSPARENT/BUFFERED
CPU ADDRESS LATCH (NOTE 1)
+5V
16/8_BIT
TRIGGER_SEL
MSB/LSB
+5V
Mini-ACE
FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION
相關(guān)PDF資料
PDF描述
BU-61843G3-140L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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