參數(shù)資料
型號(hào)： BT458LPJ80
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁(yè)數(shù)： 34/60頁(yè)
文件大?。?/td> 647K
代理商： BT458LPJ80
4.0 Application Information
Bt457/Bt458
4.1 Clock Interfacing
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
4-2
Conexant
L45801 Rev. N
Applications of 165 MHz require robust ECL clock signals with strong
pulldown (
–
20 mA at VOH) and double termination for clock trace lengths
greater than 2 inches.
The CLOCK and CLOCK* inputs must be differential signals and greater
than 0.6 V peak to peak because of the noise margins of the CMOS process. The
Bt457/458 will not function if it uses a single-ended clock with CLOCK*
connected to ground.
Typically, LD* is generated by dividing CLOCK by 4 or 5 (depending on
whether 4:1 or 5:1 multiplexing was specified) and translating the result to TTL
levels. As LD* can be phase shifted relative to CLOCK, propagation delays need
not be considered when the LD* signal is derived. LD* can be used as the shift
clock for the video DRAMs and to generate the fundamental video timing of the
system (e.g., SYNC* and BLANK*).
It is recommended that the Bt438 or Bt439 Clock Generator Chips be used to
generate the clock and load signals. Both support the 4:1 and 5:1 input
multiplexing of the Bt457/458, and set the pipeline delay of the Bt457 and Bt458
to eight clock cycles.
Figure 4-1
and
Figure 4-2
illustrate use of the Bt438 with
the Bt457/458.
When a single Bt457 is used, the PLL output is ignored and should be
connected to GND (either directly or through a resistor up to 150
).
Setting the Pipeline
Delay (Bt457 and Bt458)
The pipeline delay of the Bt457/458, although fixed after a power-up condition,
can be anywhere from six to ten clock cycles. The Bt457/458 contains additional
circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438
and Bt439 Clock Generator Chips support this mode of operation when they are
used with the Bt457/458.
To reset the Bt457/458, it should be powered up with LD*, CLOCK, and
CLOCK* running. The CLOCK and CLOCK* signals should be stopped with
CLOCK high and CLOCK* low for at least three rising edges of LD*. The device
can be held with CLOCK and CLOCK* stopped for an unlimited time.
Figure 4-2. Generating the Bt457 Signals (Monochrome Application)
+5V
14
MONITOR
PRODUCTS
970E
7
220
330
+5V
220
220
150
0.1
1K
VAA
CLOCK
CLOCK*
LDA
VREF
CLOCK
CLOCK*
LDA*
VREF
Bt438
Bt457
457-8_008
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